Committee:
     PRESIDENT: FONTOURA DE GUSMAO CERQUEIRA, RENATO
     SECRETARI: TOUS LIESA, RUBÉN
     VOCAL: DE MORAES, RAFAEL JESUS
Thesis abstract: The Oil and Gas (O&G) industry ranks prominently among the leading commercial users of powerful supercomputers worldwide, as indicated by global High-Performance Computing (HPC) ranking lists, such as TOP500 and Green500. Geoscience applications, particularly flow and geomechanical simulators, pose demanding workloads for HPC in adressing complex engineering challenges in the O&G industry, together with seismic processing. The rise of hybrid on-demand and cloud HPC environments presents new challenges to end users. Beyond expertise in their fields, users must navigate the intricacies of computer architecture to select the optimal hardware and parallelization option. They also need to consider the business model decisions of the cloud providers, such as managing spot instances, selecting different cloud regions, or even different cloud providers.Furthermore, users struggle with the complexities of configuring their own geoscience software due to the multitude of tunable numerical parameters. Default values may not be optimal for specific reservoir models, requiring geoscientists’ expertise in both the physics and mathematics behind the simulators and in computer science. A deep understanding of application performance is challenging, as it can vary based on input parameters. Many users end up relying on default configurations or decisions by system administrators for geoscience software, missing opportunities to optimize speed and cost-effectiveness.This thesis aims to shift the paradigm in utilizing HPC for geoscience by entrusting computer architecture decisions to domain-aware optimization algorithms. Such an approach not only enhances usability for the end user, but can also translate into substantial reductions in both time and cost. These algorithms could lead to better utilization of on-premises supercomputers and cost optimization of cloud resources. We evaluate the feasibility of this approach through the contributions of three algorithms. The first algorithm of this work was named TunaOil, which is a novel methodology that uses previous reservoir simulation executions to train an oracle that proposes near-optimal numerical parameters for subsequent simulations within a History Matching (HM) workflow. This allows the simulation parameters to be adjusted without additional executions, saving valuable time. Experiments show that the contribution of this algorithm is an improvement of up to 31% in the overall runtime of the HM workflow.The second algorithm, named MScheduler, is a metascheduler framework designed for reservoir simulations in the cloud. It effi-ciently executes SLURM jobs by utilizing spot Virtual Machines (VMs) to minimize costs and ensure job completion even in the event of VM termination. Key contributions include a novel methodology for reservoir simulation checkpointing, a cost-based scheduler, and an analysis of the strategy using real production jobs. MScheduler significantly reduces financial costs with a slight increase in makespan. On average, it reduces monetary costs by up to 32%, with only an 8% increase in the makespan compared on-demand executions. In the best case, the monetary savings reach 66%, with a 19% increase in makespan.The third algorithm utilizes Machine Learning (ML) algorithms in job schedulers to predict execution times of reservoir job, improving cluster resource efficiency. The developed model classifies the duration time interval of SLURM reservoir simulation jobs with an accuracy of more than 70%, exceeding the standard performance described in the job scheduling literature, thus contributing to improved scheduling decisions.Together, these algorithms mark a paradigm shift in HPC utilization for geoscience applications. They liberate end users from complex computer architecture choices, contributing to improved decision-making and significant time and cost benefits.

Committee:
     PRESIDENT: BULL, JONATHAN MARK
     SECRETARI: JIMENEZ GONZALEZ, DANIEL
     VOCAL: ARAUJO, GUIDO
Thesis abstract: In HPC, task-based models have gained prominence via the adoption of tasks in OpenMP, as an asynchronous and platform-agnostic high-performance and productive model by annotating existing code, transforming it into a parallel version. A program is expressed as a Directed Acyclic Graph (DAG), whose vertices are units of code called tasks. Edges between tasks represent dependencies between them, and tasks with no logical relationship can be executed concurrently. The task graph is independent of the targeted platform architecture, making these models suitable for concurrent execution on a broad spectrum of platforms such as multi-core SMPs or offloaded to GPUs, FPGAs, or accelerators. Several initiatives explore distributed-tasking approaches, which use the task model to decompose the application across multiple nodes with distributed memory. The advantage is that the application is expressed in a simple and clean manner that reflects only the computations and dependencies. Unfortunately, the distributed tasking approaches suffer from poor efficiency and scalability, which hinder their adoption by the HPC community. This is mainly due to the overhead of task creation and dependency graph construction, which are usually sequential. This thesis proposes two techniques to address this problem. Our first approach relates to task nesting, which mitigates the sequential bottleneck by building the full dependency graph in parallel using multiple concurrently executing parent tasks. A key limitation of task nesting is that a task cannot be created until all its accesses and its descendants’ accesses are known. Current approaches to work around this limitation either halt task creation and execution using an explicit taskwait barrier or substitute dependencies with artificial accesses known as sentinels. We introduce the auto clause, which indicates that the task may create subtasks that access unspecified memory regions, or it may allocate and return memory at addresses that are not yet known. Contrary to taskwait, our approach does not prevent the concurrent creation and execution of tasks, maintaining parallelism and allowing the scheduler to optimize load balance and data locality. In addition, all tasks can be given a precise specification of their own data accesses, unlike sentinels, resulting in a unified mechanism governing task ordering, program data transfers on distributed memory, and optimizing data locality, e.g. on NUMA systems. The auto clause, therefore, provides an incremental path to develop programs with nested tasks by removing the need for every parent task to have a complete specification of the accesses of its descendent tasks while reducing redundant information that can be time-consuming and error-prone to describe. Our second approach takes advantage of the iterative behaviour of many HPC applications, such as those that employ iterative methods or multi-step simulations. Most models construct the full unrolled task graph sequentially despite the fact that these applications create the same directed acyclic graph of tasks on each timestep. We define the programming model based on the taskiter clause, a recently introduced construct in the literature for iterative applications on SMP. We also describe the full runtime implementation to exploit this information to eliminate the sequential bottleneck and control messages while retaining the simplicity and productivity of the existing approach. We integrate both techniques into OmpSs-2@Cluster, the distributed tasking variant of OmpSs-2, and evaluate the performance on the MareNostrum 4 supercomputer.

Committee:
     PRESIDENT: MARZO LAZARO, JOSE LUIS
     SECRETARI: BARLET ROS, PERE
     VOCAL: NIN GUERRERO, JORDI
Thesis abstract: This research addresses resource allocation in communication networks, with emphasis on the impact of human uncertainty on the performance of these networks, especially those using advanced technologies. The central hypothesis of this thesis is that variations in human behavior influence the operational efficiency of communication networks. To validate this hypothesis, a methodology has been designed that includes an exhaustive review of the specialized literature, complemented with a rigorous qualitative and quantitative analysis in simulated scenarios.In this context, a specific case study is investigated: the use of mobile applications for rented vehicles with driver, such as Uber and Cabify, operating in a network slice of a 5G network. These applications, installed on mobile devices, facilitate the connection between users and drivers, showing the availability of vehicles in real time. The process begins when a user selects an origin and destination point in the app, which proposes an optimal route. However, the driver can modify the proposed route without penalty, introducing uncertainty that can negatively affect network performance.In the simulations, special attention is paid to the Call Drop Rate (CDR) as a function of possible failures during the handover process. The simulations are developed in multiple stages: initially in a minimum scenario, designed to verify the influence of uncertainty on network performance. In the second stage, the model is evaluated in the Simulation of Urban Mobility (SUMO) simulator, which brings more realism to the vehicular environment. This simulator is integrated with the Artery-C framework, which incorporates elements related to 5G technology. In the final phase, data from the InTAS scenario, which models detailed information of the city of Ingolstadt, is used, providing a robust test environment for model validation.The findings show the relevance of developing methodologies that optimize resource allocation and improve network performance, aligned with operators' strategic objectives. This approach represents a promising way to increase efficiency and effectiveness in the implementation of technological solutions in dynamic and complex environments.The main objective of this research is to develop and evaluate a model that captures human uncertainty from multiple perspectives, adopting an interdisciplinary approach. The results indicate that human uncertainty significantly affects the performance of communication networks. Through an interdisciplinary approach, an innovative model has been designed that integrates sociological, psychological and computational aspects, capturing human uncertainty in advanced technology contexts. The adaptability and effectiveness of the model have been corroborated using advanced computational tools.This study contributes to the field of resource allocation in communication networks, demonstrating the importance of adopting adaptive strategies. For future research, it is proposed to extend the model to analyze different network slices, considering unique characteristics and constraints imposed by service providers. This would include the evaluation of resource seasonality to improve the elasticity and responsiveness of the model. In addition, it is suggested to develop an innovative method for dynamic resource allocation that incorporates human uncertainty, allowing adaptive decisions in real time. These approaches would promote more effective management and optimization of network resources in various contexts and temporalities.

Committee:
     PRESIDENT: ANTONIU, GABRIEL
     SECRETARI: GARCÍA ALMIÑANA, JORDI
     VOCAL: TALIA, DOMENICO
Thesis abstract: Efficient data management is a fundamental aspect of application workflows, particularly in the context of High-Performance Computing environments. This thesis examines the potential of object stores as a robust candidate for HPC storage systems.The first contribution of this thesis is the conditioning of a distributed object store combined with the architectural design of its integration with a computational framework. The resulting object store can efficiently use HPC resources. This is achieved by leveraging active capabilities and results in an increase of data locality and execution performance.After this first contribution --the fruit of which is a software stack architecture, in addition to its evaluation characterization-- we propose two additional distinct contributions (second and third contributions of this thesis) that showcase the potential of such an active object store in the realm of HPC. For the second contribution, we introduce a new software mechanism for iterating datasets and performing distributed execution on this software stack. Our proposal is able to abstract the relationship between data distribution and task distribution while delivering performance benefits in a wide variety of scenarios. This is achieved without sacrificing the programmability of the task based programming model.The third contribution of this thesis is related to the integration of a hardware technology, the non-volatile memory (NVM). The main idea is to leverage the active aspect of the object store and combine it with the byte-addressable nature of these new kind of memories. The characteristics of NVM allow to perform in-place computation --without needing to stage-in data from this persistent memory layer-- and the active mechanism is able to invoke the execution next to its data. These two aspects intertwine and allow the object store to manage NVM space while boosting data locality and reducing overall memory footprint.All contributions are implemented as part of dataClay (the storage system, an object store). This thesis includes the implementation and evaluation of these proposals with commonly used scientific applications. In addition to completing and evaluating the integration of dataClay and COMPSs (the execution framework), the software mechanisms for iterating datasets are also implemented and evaluated with Dask (another task-based execution framework). The different scenarios explored showcase the benefits that our contributions bring to the proposed software stacks within the HPC ecosystem.

Committee:
     PRESIDENT: SCARSELLI, FRANCO
     SECRETARI: SPADARO, SALVATORE
     VOCAL: PERINO, DIEGO
Thesis abstract: In the wake of a digital revolution, contemporary society finds itself entrenched in an era where network applications' demands surpass the capabilities of conventional network management solutions. This dissertation navigates through the intricacies of modern networked environments, where traditional management approaches are falling short due to emerging applications like augmented and virtual reality, holographic telepresence, and vehicular networks, demanding ultra-low latency and robust adaptability. These evolving networks form the backbone of modern society, sustaining numerous vital services but posing elevated complexity and operational hurdles for Internet Service Providers (ISPs) and network operators.Amidst this complexity, the need for innovative solutions to optimize and manage today's networks is more pronounced than ever. A central proposition of this dissertation is the MAGNNETO framework, a groundbreaking Machine Learning (ML) based initiative that stands for Multi-Agent Graph Neural Network Optimization. This framework is at the heart of the endeavour to facilitate distributed optimization in networked scenarios. By integrating a Graph Neural Network (GNN) architecture into a Multi-Agent Reinforcement Learning (MARL) setting, it instigates a fully distributed optimization process and capitalizes on the inherent distributed nature of networked environments, hence potentially addressing scalability issues and facilitating real-time applications. This initiative is adaptable, offering versatility in addressing various use cases and showcasing robustness to meet the challenging requisites of real-world applications.A substantial contribution of this work is the successful implementation of MAGNNETO across different relevant networked cases, prominently focusing on two highly impactful scenarios within the computer network field. Initially, it re-examines the pivotal issue of Traffic Engineering (TE) optimization in ISP networks. With the goal of curtailing network congestion, MAGNNETO-TE is introduced, a variant of the framework specifically devised to minimize maximum link utilization in these networks. Remarkably, this adaptation heralds a paradigm shift by equalling the performance of traditional state-of-the-art TE optimizers but at a fraction of the execution cost.Moreover, the research explores the complex sphere of Congestion Control (CC) in Datacenter Networks (DCN), another critical service in our current digital world that is characterized by dynamic traffic patterns and stringent low-latency prerequisites. Here, MAGNNETO-CC emerges as a potent solution, offering an offline, distributed strategy that harmonizes with widely deployed CC protocols, surpassing other state-of-the-art ML-based CC methodologies and prevailing static CC configurations in performance.Looking ahead, the dissertation also delineates potential avenues to enhance MAGNNETO, particularly addressing challenges tied to current GNN architectures (e.g. over-smoothing and over-squashing). It envisions integrating Topological Deep Learning (TDL) techniques to foster a novel, promising approach to distributed optimization that has the potential to exploit arbitrary multi-element correlations, going beyond the traditional graph domain. By addressing the urgent need for efficient network traffic storage on networks with multiple vantage points, the proposed topological-inspired methodology reveals itself as a robust ML-based baseline for lossy data compression.In summation, this dissertation embarks on a pioneering journey to confront the elemental challenges of optimizing networked, graph-based systems. It unfurls the innovative MAGNNETO solution as a beacon of versatility and adaptability, displays its multifaceted applications, and heralds promising directions for future research, aiming to redefine the landscape of distributed network optimization and management in this digitally transformative era.

Committee:
     PRESIDENT: CASELLAS REGI, RAMON
     SECRETARI: COMELLAS COLOME, JAUME
     VOCAL: SAMBO, NICOLA
Thesis abstract: Optical transport networks (OTNs) are a core infrastructure and key-enabler of today’s hyper-connected society as most of the Internet data traffic is transferred over optical fibers. Traffic demand is experiencing rest-less growth as Internet-services are reaching increasing audience and capacity-hungry applications are arising (e.g., industry 4.0). In view of this, constant innovation is required in OTNs to accommodate the requested capacity while minimizing the cost. In this scenario, digital twins (DTs) – intended as a combination of models self-adjusting with their physical counterpart and of algorithms acting on the network for specific applications – are being proposed as a solution for: 1) maximizing the transport capacity by reducing the network margins; 2) pave the way towards optical network automation. The main objective of this PhD Thesis is to improve network operation based on the use of DTs algorithms and models for failure management, lightpath provisioning and optical amplifier control. To achieve this goal, different machine learning (ML) algorithms were investigated and the capabilities of the OCATA DT were extended. This main goal is achieved by the following three specific goals:1. Applications of Optical Layer DT During Network Operation. The OCATA capabilities are extended for quality of transmission (QoT) estimation and failure management. Tailor-made features are extracted from IQ constellation samples, which show correlations with QoT metrics and with failures-induced signal degradations. Next, specific ML-based models and algorithms for QoT estimation, soft-failure detection, identification and severity estimation are proposed. Results from both simulation and experiments show noticeable accuracy on the estimation of QoT and on the prediction of failures affecting the transmitter, optical filters and amplifiers. Furthermore, this approach was confirmed also for detecting and identifying spectrum anomalies. 2. Applications of Optical Layer DT for Lightpath Provisioning. OCATA capabilities are extended for modulation formats besides 16-quadrature amplitude modulation (QAM) and for digital subcarrier multiplexing signals (DSCM). Firstly, an algorithm for lightpath provisioning is proposed and evaluated based on simulations. Secondly, I experimentally evaluate its accuracy to predict the impact of optical filtering penalties. The simulations show an overall high accuracy for different signal formats and demonstrate their viability for lightpath provisioning. Moreover, the models showed the most advantageous trade-off between accuracy and execution time when compared with other existing methods. Finally, the experimental results demonstrate the feasibility of implementing such models to perform quality of transmission estimation for DSCM signals.3. Application of Optical Layer DT for Amplifier Control. DT models were designed to assist a network controller in performing informed decisions when re-configuring dynamically optical amplifiers under varying channel loadings. Experimental characterization processes were performed on pluggable EDFAs. Then, ML models based on deep learning (DL) and ensemble methods were compared in terms of accuracy and computation speed. After time-consuming hyper parameter optimization (HPO) procedures, DL models showed to achieve both the best performance on the training data set and the best generalizability on unknown dataset. Furthermore, it was shown that substantial generalization error reduction can be achieved employing transfer learning (TL) techniques.

Committee:
     PRESIDENT: SIDDIQUI, MUHAMMAD SHUAIB
     SECRETARI: BERRAL GARCÍA, JOSEP LLUÍS
     VOCAL: TABATABAEIMEHR, FATEMEHSADAT
Thesis abstract: Sensor Networks (SN) will play an integral role in Beyond 5G (B5G) ecosystems, especially for highly-distributed use cases and services such as Digital Twins (DT). Thus, the underlying transport network needs to provide connectivity between the highly dense and distributed SNs and the DT manager, that typically runs far from sensor data sources, i.e., in a centralized server. In view of this, critical requirements such as high data throughput, latency sensitivity communication, and data veracity and integrity assurance are essential to be provided by B5G networks to support DT services. In order to meet such requirements, statistical and Artificial Intelligence (AI)-based SN data collection and analysis can be implemented to provide smart and efficient data transmission. By means of those procedures, SN data can be compressed and analyzed locally in order to reduce the total data volume to be conveyed in the centralized server. In addition, the inherent nature of the compression and analysis algorithms add privacy and security to the transmitted data without affecting integrity. The use of these kind of AI-based techniques opens the opportunity to perform Knowledge Transfer (KT) between DTs operating under the same tenant infrastructures. Since sharing raw data poses a privacy breach, AI-based methods allow interchanging relevant information while obfuscating critical details, thus enabling coordinated operation across differentiated segments.This Ph.D. thesis aims at enhancing the operation of dense SNs, which are supported by an underlying transport infrastructure that includes edge/fog computing capabilities distributed among nodes. Through the application of statistical and AI-based methods and procedures, the proposed methods will target several objectives, such as reducing the volume of data transported through the network while keeping privacy and integrity, detecting anomalies or events in the collected data to provide early alarms and notifications, and facilitating the operation of services across several SN domains.In more detail, the first objective is to develop methods to reduce the volume of collected sensor data through statistical and AI-based methods for data compression and sampling rate manipulation. We proposed both statistical-based and Autoencoder (AE)-based approaches for compression, as wells as sampling rate adaptation method that works with either. Simulations of implemented algorithms on real world datasets showed a significant ability to reduce the volume of the data, reaching 1% of its original size in some cases, and leading the reduced energy consumption in the factor of one-tenth in case of sensors with limited energy availability.The second objective is to develop methods for maintaining data veracity through employing AI-based anomaly detection methods at multiple levels of the network. Anomalies may arise due to a range of factors from faulty sensors to malicious attacks and detecting them can facilitate timely actions to avoid or mitigate their effect. We proposed two AE-based methods: one operating at the sensor level, and the other on the network level. Simulations of implemented algorithms on real world datasets showed more than 90% of accuracy in detecting anomalies in single sensor data analysis. Moreover, prompt detection of subtle anomalies spanning multiple sensors that could not be detected by single sensor data analysis was achieved.Finally, the third objective is to investigate methods to improve multi-domain DT systems management and coordination through KT while preserving the privacy of each individual DT. We proposed an AE-based knowledge extraction method that extracts codified information about the state of the sharing DT and sends it to the target DT. The method showed that the target DT is able to use the codified and private information about the state of the sharing DT before the changes are apparent through their effect on its system.

Committee:
     PRESIDENT: ACACIO SÁNCHEZ, MANUEL EUGENIO
     SECRETARI: MORETÓ PLANAS, MIQUEL
     VOCAL NO PRESENCIAL: JONES, TIMOTHY
Thesis abstract: Autonomous Driving Systems (ADS) are at the cusp of large-scale adoption, promising accident reduction and market potential. However, the complex software and sensor data pressure for better hardware support in this safety-critical scenario, where high performance is mandatory to meet latency deadlines. Additionally, energy efficiency, cost, and volume must also be first-class for market feasibility, calling computer architects into action.To enrich hardware support for ADS, we carry out a performance and power characterization of Autoware.ai, a state-of-the-art ADS software stack. We find significant time spent processing Light Imaging Detection and Ranging (LiDAR) sensor data, which are widely used by ADS. LiDAR captures 3D point clouds for tasks such as segmentation, localization, and object detection.Despite its importance, hardware support for LiDAR has only recently gained traction. Further, while most point cloud processing algorithms run on CPUs, recent works propose costly hardware accelerators. Instead, we aim to use existing general-purpose hardware and software for point cloud processing with minor CPU augmentations. For that, we introduce a small set of CPU instructions targeting point cloud neighbor search based on k-d trees, a key operation used in various algorithms.The first technique we propose is K-D Bonsai, which reduces data movement during the neighbor search by compressing k-d tree leaves in execution time, exploiting value similarity. K-D Bonsai further compresses the data using a reduced floating-point representation, exploiting the physically limited range of point cloud values collected with LiDAR. We implement K-D Bonsai through a small set of new CPU instructions to compress, decompress, and operate on points. To maintain baseline accuracy,we carefully craft the instructions to detect precision loss due to compression, allowing re-computation in full precision to take place if necessary. Therefore, K-D Bonsai reduces data movement, improving performance and energy efficiency while guaranteeing baseline accuracy and programmability. K-D Bonsai improves the end-to-end latency of the segmentation task of Autoware.ai by 9.26% on average, 12.19% in tail latency, and reduces energy consumption by 10.84%. Unlike the expensive accelerators proposed in related work, K-D Bonsai improves neighbor search with minimal area increase (0.36%).In the second technique, we found that consecutive neighbor search queries are often similar, visiting k-d tree nodes with considerable resemblance. We leverage this observation to cheaply speed up neighbor search with the available CPU Vector Processing Unit (VPU). We propose a hardware/software co-design called Caravan. At the software level, Caravan- SW exploits search similarity, gathering consecutive queries to search for their neighbors in parallel with SIMD instructions. Yet, when the navigation of queries diverges, particularly in the deeper levels of the k-d tree, Caravan-SW faces sparsity and the VPU lanes are underutilized. We tackle this with Caravan-HW, adding two new instructions that re-index valid vector elements and allow fast operand shuffling and dense SIMD operations to take place, suppressing the hard-to-predict runtime sparsity of Caravan-SW.With AVX512, Caravan-SW speeds up neighbor search by 4.05× (1.85× end-to-end) in Autoware.ai point cloud segmentation.With the additional Caravan-HW support, the leaf processing part of neighbor search can be further optimized, boosting gains to 5.19× (1.97× end-to-end), with minimal area costs. Our programmable and minimally intrusive solution has end-to-end benefits comparable to accelerators.

Committee:
     PRESIDENT: PESCAPÈ, ANTONIO
     SECRETARI: ARIAS VICENTE, MARTA
     VOCAL: RÉTVÁRI, GÁBOR
Thesis abstract: Network modeling is central to the field of computer networks. Models are useful in researching new protocols and mechanisms, allowing administrators to estimate their performance before their actual deployment in production networks. Network models also help to find optimal network configurations, without the need to test them in production networks. Arguably, the most prevalent way to build these network models is through the use of discrete event simulation (DES) methodologies which provide excellent accuracy. State-of-the-art network simulators include a wide range of network, transport, and routing protocols, and are able to simulate realistic scenarios. However, this comes at a very high computational cost that depends linearly on the number of packets being simulated. As a result, they are impractical in scenarios with realistic traffic volumes or large topologies. In addition, and because they are computationally expensive, they do not work well in real-time scenarios.Another network modeling alternative is Queuing Theory (QT) where networks are represented as inter-connected queues that are evaluated analytically. While QT solves the main limitation of DES, it imposes strong assumptions on the packet arrival process, which typically do not hold in real networks.In this context, Machine Learning (ML) has recently emerged as a practical solution to achieve data-driven models that can learn complex traffic models while being extremely accurate and fast. More specifically, Graph Neural Networks (GNNs) have emerged as an excellent tool for modeling graph-structured data showing outstanding accuracy when applied to computer networks. However, some challenges still persist:1. Queues and Scheduling Policies: Modeling queues, scheduling policies, and Quality-of-Service (QoS) mappings within GNN architectures poses another challenge, as these elements are fundamental to network behavior.2. Traffic Models: Accurately modeling realistic traffic patterns, which exhibit strong autocorrelation and heavy tails, remains a challenge for GNN-based solutions.3. Training and Generalization: ML models, including GNNs, require representative training data that covers diverse network operational scenarios. Creating such datasets from real production networks is unfeasible, necessitating controlled testbeds. The challenge lies in designing GNNs capable of accurate estimation in unseen networks, encompassing different topologies, traffic, and configurations.4. Generalization to Larger Networks: Real-world networks are often significantly larger than testbeds. Scaling GNNs to handle networks with hundreds or thousands of nodes is a pressing challenge, one that requires leveraging domain-specific network knowledge and novel architectural approaches.This dissertation represents a step forward in harnessing Graph Neural Networks (GNN models) for network modeling, by proposing a new GNN-based architecture with a focus on addressing these critical challenges while being fast and accurate.

Committee:
     PRESIDENT: ZENNARO, MARCO
     SECRETARI: MACCARI, LEONARDO
     VOCAL: FILIPPINI, ILARIO
Thesis abstract: This thesis aims to investigate the efficacy and applicability of Wireless Backhaul Network (WBN) in two divergent contexts: ultra-dense urban networks for 5G and connectivity solutions for rural or digitally divided areas. WBN offer an adaptable and resilient framework for data transmission, making them an attractive option for the next generation of wireless networks, particularly 5G. In dense urban settings, where the demand for high data rates is pressing, wireless mesh backhauls can serve as a strategic asset in achieving the promised data throughput for 5G networks. These networks inherently require a dense deployment of nodes to deliver on their promise of high-speed, low-latency communication. Therefore, we analyze the role that wireless mesh backhauls can play in such densely populated areas, emphasizing their potential to meet or even exceed 5G’s high data rate expectations.Conversely, in rural or digitally divided areas, the economic feasibility of deploying traditional last-mile copper or fiber-optic networks often proves to be prohibitive. In such cases, WBN, deployed either as Wireless Community Network (WCN) or as part of a Wireless Internet Service Provider (WISP)’s infrastructure, can offer a viable alternative. This technology could bridge the digital divide by providing robust, cost-effective internet connectivity to underserved regions.To substantiate my findings, I leveraged Geographic Information Systems (GIS) technology and GPU-based computational methods together with graph analysis and simulations. GIS technology, leveraging different open datasets such as Digital Surface Models (DSM) and vectorial maps, make a detailed understanding of the geographical landscape possible, crucial for building detailed feasibility models in various environments. GPU-based computational methods accelerate the model analysis, enabling an in-depth evaluation within a reasonable timeframe. As a result I was able to optimize various network aspects, such as node placement, network topology and energy consumption, which are critical parameters for the effective deployment of these networks.This work integrates these computational methods and technologies to offer a comprehensive view of how wireless mesh backhauls can be efficiently deployed in both urban and rural settings. The results offer valuable insights into the network architecture best suited for each context, with particular attention to scalability and resiliency. In summary, this thesis contributes to a broader understanding of the potential that wireless mesh backhauls hold in addressing the connectivity requirements of diverse settings, ranging from the ultra-dense urban environment required for 5G to the unique challenges posed by rural and digitally divided regions.

Committee:
     PRESIDENT: GARCÍA LÓPEZ, PEDRO
     SECRETARI: RUIZ RAMÍREZ, MARC
     VOCAL: CIRILLO, DAVIDE
Thesis abstract: In recent years, the exponential increase of generated data has raised the need for implementing new methodologies to process the huge datasets being created. High-Performance Computing (HPC) brings together a set of technologies mainly based on parallel computing that help reduce the time expended analyzing these datasets. A research field where these technologies are needed is Computational Genomics. Furthermore, the complexity of the genomic datasets limits the use of basic conventional methods for the discovery of complex significant relations, introducing the need for Machine learning (ML) algorithms and robust statistical methods to better classify these variants. In the first part of the thesis, we aim to identify complex patterns of somatic genomic rearrangements in cancer samples, which are triggered by internal cellular processes and environmental factors. The problem of classification becomes particularly challenging when considering thousands of rearrangements at a time, often composed of multiple DNA breaks, increasing the difficulty in classifying and interpreting them functionally. Here we present a new statistical approach to analyze structural variants (SVs) from 2,392 tumor samples from the Pan-Cancer Analysis of Whole Genomes (PCAWG) Consortium and identify significant recurrence. The proposed methodology is able not only to identify complex patterns of SVs across different cancer types but also to prove them as not random occurrences, identifying a new class of pattern composed of three SVs that was not previously described. In the second part of the thesis, we approach another challenge of human genetics, which is the study of the relation between single nucleotide variants (SNVs) and complex diseases, such as Type 2 Diabetes, Asthma, or Alzheimer's. The study of these disease-variant associations is usually performed in a single independent manner, disregarding the possible effect derived from the interaction between genomic variants. Here, we have created a containerized framework that uses Multifactor Dimensionality Reduction (MDR) to detect combinations of variants associated with Type 2 Diabetes (T2D), called Variant Interaction Analysis (VIA). This methodology has been tested in the Northwestern University NUgene project cohort using a subset of 1,883,192 variant pairs with some degree of association with T2D and identifying a subset of 104 significant pairs, two exhibiting a potential functional relationship with T2D. The developed algorithm has been released in an open-source repository, including the containerized HPC framework, which can be used to search for significant pairwise interactions in other datasets.In both frameworks developed within the thesis, the use of large-scale supercomputing architectures has been a hard requirement to find relevant clinical indicators. To ensure open and broad access to HPC technologies, governments, and academia are pushing toward the introduction of novel computing architectures in large-scale scientific environments. This is the case of RISC-V, an emerging open standard instruction-set architecture. To evaluate such technologies, in the last two parts of the thesis, we propose the use of our VIA use case as a benchmarking, providing the first genomic application for RISC-V. With this use case, we provide a representative case for heavy ETL (Extract, Transform, Load) data processing. We developed a version of the VIA workload for RISC-V and adapted our implementation in x86-based supercomputers (e.g. Marenostrum IV at the Barcelona Supercomputing Center (BSC)) to make a fair comparison with RISC-V, since some technologies are not available there. With this benchmark, we have been able to indicate the challenges and opportunities for the next RISC-V developments and designs to come, from a first comparison between x86 and RISC-V architectures on genomic workload executions over real hardware implementations.

Committee:
     PRESIDENT: PETERSEN MOURA TRANCOSO, PEDRO
     SECRETARI: JIMENEZ GONZALEZ, DANIEL
     VOCAL: GOMEZ LUNA, JUAN
Thesis abstract: The continuous progress of Moore’s Law in improving single-threaded performance (executiontime) through clock frequency and process node improvements has slowed down due to physicallimitations in silicon device physics. This has resulted in a shift towards using multicoreprocessors to achieve performance gains. However, the use of multiprocessing is limitedby Amdahl’s Law, in which the sequential parts of the applications restrict the speedups inparallel systems. Consequently, the technology industry is now emphasizing specialization anddeveloping domain-specific accelerators to enhance performance compared to general-purposecomputers.Genomics is a field that deals with the study of genes and their functions. Thanks to currentand ongoing advancements, each stage of development in sequencing technologies is able toproduce enormous amounts of data at an increasingly faster and cheaper way compared to itsprevious stage. However, the assembly and analysis of this data take extensive time on general-purpose processors, and the processor performance is growing at a much slower pace thanthe DNA sequencing speed. Hence, domain-specific accelerators are becoming increasinglyessential in the genomics field, especially for DNA assembly. Specialized hardware computingdevices designed for this specific domain can achieve significant performance improvementscompared to general-purpose computers. Thus, with domain-specific accelerators, the speed ofDNA assembly can keep up with the pace of DNA sequencing, allowing for quicker analysisand discoveries in the genomics field.The main goal of this thesis is to accelerate two critical applications of DNA assembly,k-mer counting and pairwise read alignment, using FPGAs and ASICs. The first contribution ofthis thesis targets accelerating the k-mer counting application using FPGAs and its adaptationin a genomics application called SMUFIN, a Somatic MUtation FINder. The second andthird contributions focus on exploiting FPGAs for accelerating the Wavefront Alignment(WFA), a novel pairwise read alignment algorithm for aligning DNA sequences generated bydifferent sequencing technologies. The accelerator in the second contribution is customized forshort DNA sequences of up to 300 bases, which are generated by next generation sequencingtechnologies, while the accelerator in the third contribution is customized for long DNAsequences of up to 50K bases, which are generated by third generation sequencing technologies.The fourth contribution proposes an ASIC accelerator of the WFA algorithm and its integrationin a RISC-V SoC. In all contributions, we analyze different parts of the application and portthe most time-consuming parts to the accelerator. We also modify and re-design the remainingCPU parts to better adapt them to the accelerator code and finally propose efficient co-designedaccelerated designs.In our first contribution, the integration of our k-mer counting accelerator improves theSMUFIN k-mer counting performance by 2.14× while consuming 2.93× less energy and1.57× less memory compared to the baseline multi-threaded software implementation. Theperformance of the WFA accelerators in the second and third contributions is evaluated usingone and two FPGAs. Compared to the baseline multi-threaded software implementation of theWFA running on a IBM POWER9 high-performance processor, our WFA accelerator for shortreads reaches performance improvements of up to 8.8× and 13.5× with one and two FPGAs,respectively. The WFA accelerator for long reads reaches performance improvementsof up to 5.6× and 9.9× with one and two FPGAs, respectively. In our fourthcontribution, our ASIC WFA accelerator integrated in the RISC-V SoC reaches performanceimprovements of up to 1076× compared to the single-threaded software implementation of theWFA on Sargantana, the RISC-V CPU of the chip.

Committee:
     PRESIDENT: ROS BARDISA, ALBERTO
     SECRETARI: CANAL CORRETGER, RAMON
     VOCAL: PERAIS, ARTHUR
Thesis abstract: Since its inception with the first computing systems, computer architecture has lived through many revolutions and saw plenty of technological innovations. However, a significant challenge has persisted throughout the evolution of computing systems: the Memory Wall. To address this challenge, architects have devised various latency tolerance techniques, including cache hierarchy, cache replacement policies, hardware prefetching, and off-chip prediction. Cache hierarchy involves the use of intermediate memories, such as caches, to store frequently accessed data close to the processor, thereby reducing memory access latencies. Cache replacement policies determine which data blocks should be stored or evicted from caches based on predictions of future reuse. Hardware prefetching mechanisms aim to bring data blocks that are likely to be needed in the near future into the cache proactively. Off-chip prediction predicts whether a load demand request will benefit from cache access or if it will require a DRAM access, allowing for speculative fetching of data blocks from DRAM to hide memory access latencies. This thesis addresses the challenges of cache management and memory access optimization in modern computer architectures, focusing on improving performance and energy efficiency across a variety of workloads. It presents three main contributions. The first contribution critically assesses the effectiveness of contemporary Last Level Cache (LLC) replacement policies across a diverse spectrum of workloads, encompassing graph processing, scientific, industrial applications, as well as standard benchmark suites like SPEC CPU 2006 and SPEC CPU 2017. Despite exhibiting notable performance enhancements in conventional benchmark scenarios, these existing LLC replacement policies often falter in capturing the nuanced access patterns characteristic of modern High-Performance Computing (HPC) and big data workloads. In response to this challenge, two novel LLC replacement policies, namely Multi-Sampler Multiperspective (MS-MPPPB) and Multiperspective with Dynamic Features Selector (DS-MPPPB), are introduced and rigorously evaluated. Demonstrating superior efficacy across a broad array of workloads, these innovative policies offer heightened performance benefits tailored specifically for HPC and big data applications. The second contribution is dedicated to enhancing memory access patterns, specifically for graph-processing workloads. These workloads are renowned for their irregular memory access patterns and suboptimal data locality. This contribution targets the first level of the cache hierarchy, as careful analysis reveals that, when considering graph-processing workloads, the vast majority of L1D misses eventually require a DRAM access. Introducing the innovative Large Predictor (LP), this endeavor aims to discern between regular and irregular memory accesses, channeling irregular accesses efficiently through a dedicated Side Data Cache (SDC). By synergizing LP with SDC, notable performance enhancements are achieved, surpassing conventional cache hierarchies and state-of-the-art cache replacement policies, particularly within the realm of graph-processing applications. The third contribution presents the Two Level Perceptron (TLP) predictor, a sophisticated approach that integrates off-chip prediction with adaptive prefetch filtering within the first-level data cache (L1D). Leveraging a dual-layered structure composed of the First Level Predictor (FLP) and Second Level Predictor (SLP), TLP effectively mitigates average DRAM transactions while enhancing overall performance across both single-core and multi-core workloads. Collectively, these contributions advance the state-of-the-art in cache management and memory access optimization, providing insights and techniques to enhance the performance and energy efficiency of modern computer architectures across a variety of workloads.

Committee:
     PRESIDENT: XEKALAKIS, POLYCHRONIS
     SECRETARI: JIMENEZ GONZALEZ, DANIEL
     VOCAL: DE LUCAS CASAMAYOR, ENRIQUE
Thesis abstract: Following the growing demands of applications mobile GPUs have greatly evolved in the past decade with expectations for continued advancement. These developments must address the rising performance demands and prioritize energy efficiency to accommodate the energy and temperature constraints of battery-powered, handheld devices. Main memory accesses are one of the main sources of energy consumption and occasionally a source of performance bottleneck in GPUs. The adoption of Tile-Based Rendering (TBR) architecture for many mobile GPUs in the late 1990s, marks a leap towards energy efficiency for mobile GPUs by enhancing locality and minimizing bandwidth-intensive memory accesses.The objective of this thesis is to enhance memory access efficiency in TBR GPU architectures for graphics applications. The strategy involves fine-tuning the structures in the memory hierarchy or altering the memory access patterns directed towards the memory hierarchy. By capitalizing on the unique characteristics of graphics applications, the goal is to boost both performance and energy efficiency with minimal hardware adjustments, thereby avoiding any adverse impact on general-purpose workloads running on GPUs.TBR architectures introduce an overhead through the creation of a specialized data structure for tiling which is stored in memory and cached in L1 and shared L2 caches. The OPT replacement policy, has been formally proven as optimal for minimizing misses but it is near-impossible to implement in hardware. The first proposal in this thesis brings the OPT to life, for this data structure. Along with other improvements in the L2, this proposal called TCOR results in a 13.8% decrease in the memory hierarchy energy consumption and an increased throughput in the Tiling Engine. DTexL, the second proposal in this thesis, increases the aggregated capacity of certain L1 caches by reducing replication of memory blocks. Contemporary GPUs have multiple GPU cores and a scheduler that distributes work (warps) among them, focusing on load balancing. These load balancing techniques are detrimental to texture memory locality in the L1 caches. We propose a new workload scheduler that favours texture locality and to overcome the resulting load imbalance, we propose a minor modification to the GPU architecture. DTexL results in a 46.8% decrease in L2 Accesses, a 19.3% increase in performance and a 6.3% decrease in total GPU energy. All this with a negligible overhead.Literature is plentiful in works exploiting cache locality for GPUs. A majority of them explore replacement or bypassing policies. In our third proposal, we surpass this exploration by fabricating a formal proof for a no-overhead quasi-optimal caching technique in the shared L2 for textures. We exploit the frame-to-frame reuse of textures by traversing frames in a boustrophedonic manner w.r.t. the conventional frame-to-frame tile order. We first approximate the texture access trace to a circular trace and then forge a formal proof for our proposal being optimal for such traces. We call our proposal Boustrophedonic Frames.Hiding memory latency is becoming a problem in contemporary GPUs. To address this challenge, we introduce WaSP as the final work in this thesis, a lightweight warp scheduler tailored for GPUs in graphics applications. WaSP strategically mimics prefetching by initiating a select subset of warps, termed priority warps, early in execution to reduce memory latency for subsequent warps. WaSP reduces average memory latency while maintaining locality for the majority of warps. While maximizing memory parallelism utilization, WaSP prevents saturating the caches with misses to avoid filling up the MSHRs. This approach reduces cache stalls that halt further accesses to the cache. Overall, WaSP yields a 3.9% performance speedup with a negligible overhead.

Committee:
     PRESIDENT: CANO REYES, JOSE
     SECRETARI: MARTORELL BOFILL, XAVIER
     VOCAL: TSOUTSOURAS, VASILIOS
Thesis abstract: The security of modern cryptographic schemes relies upon mathematical problems that are assumed to be hard to solve, like the Rivest-Shamir-Adleman (RSA) problem or the discrete logarithm problem over elliptic curves. Using the existing “classical” computers, all known algorithms attempting to solve these problems, would require such a big amount of computational time that will actually make the intercepted data useless by the time the attack finishes.Around 1997, Shor and Grover independently developed efficient quantum-computer algorithms that can give unprecedented speedup on certain mathematical problems. It then became evident that the advent of a large scale quantum computer can jeopardize secure communications. Nevertheless, it is still not clear whether there will exist large scale quantum computers able to break the current public key cryptographic standards. As a preemptive act, the National Institute of Standards and Technology (NIST) announced in 2015 its plans for transitioning to Post-Quantum (PQ) cryptographic algorithmic standards. The widespread adoption of the current standards , calls for further research on the efficiency and security of the PQ standards implementation on modern computing systems.This thesis intends to bridge the gap between the PQ cryptosystems’secure specification and their respectively secure and efficient implementation in advanced computing architectures.We specifically choose the PQ cryptosystem of Classic McEliece (CM), merely due to its long-standing security. CM has withstood attacks with minor modifications since its inception in 1978 and is currently a finalist of the NIST contest and has already been integrated in commercial products like VPN networks.This thesis comprises four main contributions. In the first one we present a hardware/software (HW/SW) co-design acceleration of the CM cryptosystem. The second contribution is geared towards the design and integration of custom designed and monolithic CM accelerators in a RISC-V based SoC. The third contribution strives to further optimize the performance of CM in hardware by introducing an advanced design of a monolithic accelerator for the encryption part of the CM cryptosystem. The final contribution of this thesis is moving away from a monolithic hardware accelerator and investigates the impact of vectorization by an SIMD unit on the CM application.With this thesis, we conclude a study conveyed on the CM cryptosystem, concerning its efficient hardware implementation on modern computing infrastructures. Nevertheless, there are numerous future research directions that could build on the knowledge gained as well as the hardware infrastructure designed in the context of this thesis. As such, we consider the secure implementation and side-channel mitigation on the CM hardware accelerators themselves and the performance evaluation of lightweight hardware implementations of CM.

Committee:
     PRESIDENT: PETIT, ERIC
     SECRETARI: MARTORELL BOFILL, XAVIER
     VOCAL: GARCIA, RÉMI
Thesis abstract: This dissertation explores the challenges and advancements in arithmetic representations and computations within computer architectures, focusing on the limitations of the IEEE 754 standard.Modern computing demands, driven by advancements in AI, HPC, and scientific simulations, make efficient and precise numerical representations crucial. This work investigates these challenges and proposes innovative solutions, evaluating their impact on computational efficiency and accuracy.The core problem is the inefficiencies of the IEEE 754 standard for floating-point arithmetic, which do not meet the needs of modern workloads. These inefficiencies result in higher energy consumption, inadequate precision, and suboptimal performance, especially in energy-constrained environments and high-precision applications.To address these challenges, this thesis explores various facets of arithmetic computation, from algorithmic concepts to metal and silicon structures. It introduces mechanisms to improve the adaptability of numerical representations, allowing precision adjustments according to computational tasks, resulting in more efficient circuits. Focusing on improving arithmetic performance, the thesis addresses energy consumption and highlights the importance of efficient arithmetic logic units. It also shows how these solutions can be integrated into various software frameworks, revealing a correlation between numerical requirements and internal precision, highlighting an underexploited aspect of general-purpose floating-point formats.Firstly, it develops a framework for generating Posit operators in hardware, improving accuracy and performance in tasks like image classification. The Posit Operator Framework, described in SystemVerilog, enables the construction of Multi-Layer Perceptrons for inference engines, applicable in POWER9/CAPI2 environments with FPGA acceleration.Secondly, it presents a generator for Systolic Arrays optimized for Matrix-Matrix Multiplication (MMM), showing the impact of custom hardware configurations on accuracy and energy efficiency. The MMM units are fully parametrizable and adapted to the numerical specifications of the workload, facilitated by a core generator with automated pipelining. These units allow evaluations with CAPI2 on FPGA and POWER9 systems, achieving up to two Tera floating-point operations per second. They have also demonstrated success in ASIC generation.Additionally, it establishes an open-source framework to integrate MMM units into high-level software, offering energy savings and enhanced precision for applications like AI and scientific computations. The methodology involves mapping General Matrix-Matrix Multiplication calls in BLAS libraries to our accelerators via the OpenCAPI coherent link, saturating the 22 GBps bandwidth by tuning computer formats to accommodate more Processing Elements while preserving accuracy.Finally, the resurgence of vector processing leads to a reevaluation of division algorithms, revealing opportunities to use smaller and slower computing units, allowing more units within varied energy and power budgets. This approach shows a broad Design Space Exploration. We developed an open-source EDA ASIC flow, facilitating parallel generation of multiple chip designs, enabling systematic exploration of power, performance, and area across various process design kits to identify optimal configurations.These contributions form an interdisciplinary thesis that advances solutions to computing challenges from an arithmetic perspective, overcoming the "arithmetic wall."

Committee:
     PRESIDENT: CASTELLÓ GIMENO, ADRIÁN
     SECRETARI: AYGUADÉ PARRA, EDUARD
     VOCAL: EL HAJJ, IZZAT
Thesis abstract: The rapid development in computing technology has paved the way for directive-based programming models towards a principal role in maintaining software portability of performance-critical applications. Efforts on such models involve a least engineering cost for enabling computational acceleration on multiple architectures, while programmers are only required to add meta information upon sequential code. Optimizations for obtaining the best possible efficiency, however, are often challenging. The insertions of directives by the programmer can lead to side-effects that limit the available compiler optimization possible, which could result in performance degradation. This is exacerbated when targeting asynchronous execution or multi-GPU systems, as pragmas do not automatically adapt to such mechanisms, and require expensive and time consuming code adjustment by programmers. Moreover, directive-based programming models such as OpenACC and OpenMP often prevent programmers from making additional optimizations to take advantage of the advanced architectural features of GPUs because the actual generated computation is hidden from the application developer.This dissertation explores new possibilities for optimizing directive-based code from both runtime and compilation perspectives. First, we introduce a runtime framework for OpenACC to facilitate dynamic analysis and compilation. Especially, our framework realizes automatic asynchronous execution and multi-GPU use based on the status of kernel execution and data availability while taking advantage of an on-the-fly mechanism for compilation and program optimization. We add a versatile code-translation method for multi-device utilization by which manually-optimized applications can be distributed automatically while keeping original code structure and parallelism. Second, we implement a novel flexible optimization technique that operates by inserting a code emulator phase to the tail-end of the compilation pipeline. Our tool emulates the generated code using symbolic analysis by substituting dynamic information and thus allowing for further low-level code optimizations to be applied. We implement our tool to support both CUDA and OpenACC directives as the frontend of the compilation pipeline, thus enabling low-level GPUoptimizations for OpenACC that were not previously possible. Third, we propose the use of a modern optimization technique, equality saturation, to optimize sequential code utilized in directive-based programming for GPUs. Our approach realizes less computation, less memory access, and high memory throughput simultaneously. Our fully-automated framework constructs single-assignment forms from inputs to be entirely rewritten while keeping dependencies and extracts optimal cases. Overall, we cover runtime techniques and optimization methods based on dynamic information, low-level operations, and user-level opportunities.We evaluate our proposals on the state-of-the-art GPUs and provide detailed analysis for each technique. For multi-GPU use, we show in some cases nearly linear scaling on the part of kernel execution with the NVIDIA V100 GPUs. While adaptively using multi-GPUs, the resulting performance improvements amortize the latency of GPU-to-GPU communications. Regarding low-level optimization, we demonstrate the capabilities of our tool by automating warp-level shuffle instructions that are difficult to use by even advanced GPU programmers. While evaluating our tool with a benchmark suite and complex application code, we provide a detailed study to assess the benefits of shuffle instructions across four generations of GPU architectures. Lastly, with sequential code optimization, we demonstrate a significant performance improvement on several compilers through practical benchmarks.Then, we highlight the advantages of computational reordering and emphasize the significance of memory-access order for modern GPUs.

Committee:
     PRESIDENT: SANCHEZ ARTIGAS, MARC
     SECRETARI: GUITART FERNANDEZ, JORDI
     VOCAL: TAHERKORDI, AMIRHOSEIN
Thesis abstract: Recently, serverless computing has garnered attention from academia and industry due to its on-demand resource provisioning, allowing users to focus solely on their core business logic by breaking down tasks into small stateless functions.Serverless offers benefits like a 'pay-per-use' cost model, greater flexibility, and transparent elastic resource auto-scaling.Researchers in academia and industry are increasingly exploring serverless computing's potential in complex, data-intensive analytics. These tasks, resource-heavy and highly parallel, involve significant inter-function communications. However, this shift presents challenges, requiring alignment with the specific needs and constraints of such applications. This research area is currently considered one of the most compelling areas of study. This thesis shows that it is possible to efficiently execute modern data-intensive analytics workloads, traditionally deployed in managed cloud clusters, within serverless computing environments using direct data inter-function communication and optimized performance-cost efficient resource allocation policies. To demonstrate this thesis, we first build a performance model for serverless workloads, considering data sharing, volume, and communication technologies. The model, with a relative error of 5.52%, evaluates the performance of a representative workload in serverless, analyzing task granularity and concurrency, data locality, resource allocation, and scheduling policies. Our results indicate that the performance of data-intensive analytics workloads in serverless can be up to 4.32x faster depending on how these are deployed. Furthermore, this characterization highlights inefficiencies in centralized object storage and stresses the primary importance of efficient resource use.We then introduce Floki, a data forwarding system that tackles the centralized object storage bottleneck. It enables direct communication between producer-consumer function pairs using fixed-size communication methods. Floki establishes point-to-point data channels for intra- and inter-node data transmission, allowing transparent data transfer and reducing network data copying. This workflow-oriented approach boosts performance and minimize resource requirements without restricting function placement.Our experimental evaluation, performed on the principal communication patterns in distributed systems, shows that Floki reduces the end-to-end time up to 74.95x, decreasing the most extensive data sharing time from 12.55 to 4.33 minutes, saving almost two-thirds of time. Additionally, Floki achieves up to 50,738x of resource-saving, equivalent to a memory allocation of approximately 1.9MB instead of an object storage allocation of 96GB.Finally, we investigates how to achieve efficient resource utilization in modern serverless environments and proposes Dexter, a novel resource allocation manager, leveraging serverless computing elasticity. Dexter continuously monitors application execution, dynamically allocating resources at a fine-grained level combining predictive and reactive strategies to ensure performance-cost efficiency (optimizing total runtime cost). Unlike black-box Machine Learning (ML) models, Dexter reaches a sufficiently good solution, prioritizing simplicity, generality, and ease of understanding. The proposed experimental evaluation demonstrates that our solution achieves a significant cost reduction of up to 4.65x, while improving resource efficiency up to 3.50x, when compared with the default serverless Spark resource allocation that dynamically requests exponentially more executors to accommodate pending tasks. Dexter also enables substantial resource savings, demanding up to 5.71x fewer resources. Dexter is a robust solution to new, unseen workloads, achieving up to 2.72x higher performance-cost efficiency thanks to its conservative resource scaling approach.

Committee:
     PRESIDENT NO PRESENCIAL: BULL, JONATHAN MARK
     SECRETARI: MARTORELL BOFILL, XAVIER
     VOCAL: THIBAULT, SAMUEL
Thesis abstract: Modern supercomputing systems feature thousands of computing nodes that already provide hundreds of cores. Parallelizing scientific and engineering applications to leverage all these resources has become a significant challenge for the HPC community. Any application that aims to perform well at scale must efficiently orchestrate and exploit both inter- and intra-node parallelism. Multiple programming models exist to exploit each of these parallelism classes. MPI and OpenMP are de facto standards for distributed- and shared-memory parallelism, respectively. MPI is a message-passing interface based on processes with separate virtual address spaces, while OpenMP defines thread-based and task-based interfaces for shared-memory parallelization. Applications can combine both types of programming models to take advantage of their particular benefits in a technique called hybrid parallel programming.Combining task-based and message-passing programming models is a promising hybrid approach that can provide a high-performance data-flow model without damaging the programmability of applications. An application can be represented as a set of directed acyclic graphs (DAGs) with one independent graph per process. Vertices represent tasks comprising computations and communications, edges represent the data dependencies among tasks, and the tasks from distinct processes (i.e., different DAGs) can communicate through message passing. This way, the intra- and inter-node parallelism is smoothly orchestrated through the task graphs. Moreover, this data-flow approach has other benefits: fine synchronizations through data dependencies and inter-process messages, the natural overlap and intertwining of application phases (e.g., computation and communication), and an automatic load balancing within each process. However, the current standards (e.g., MPI and OpenMP) prevent tasks from issuing communications efficiently, as severe performance and programmability issues must be tackled.This thesis designs and implements software solutions that allow task-based applications to efficiently incorporate communications inside their task graphs. We solve the well-known interoperability issues between task-based and message-passing programming models through two task-aware libraries. The two new libraries provide full support to application tasks that issue communications through task-aware communication operations, which can feature blocking or non-blocking semantics. The TAMPI library supports two-sided MPI communications (e.g., send/receive and collectives), and the TAGASPI library supports the one-sided communications (also known as RMA) provided by the GASPI interface. Furthermore, our task-aware mechanisms are generic enough to incorporate any other blocking or non-blocking interface (e.g., for GPU offloading) with task-based models.Our hybrid data-flow approach, which combines tasking and message passing, provides performance, scalability, and programmability for task-based applications on highly parallel systems. We demonstrate these benefits by porting several benchmarks and applications and comparing our approach with other state-of-the-art techniques.

Committee:
     PRESIDENT: QUINTANA ORTI, ENRIQUE SALVADOR
     SECRETARI: ARMEJACH SANOSA, ADRIÀ
     VOCAL: VALLEJO GUTIÉRREZ, ENRIQUE
Thesis abstract: Recurrent neural networks (RNN) have succeeded remarkably in various domains, such as Automatic Speech Recognition, Sentiment Analysis, time-series prediction, and Machine Translation. Despite their versatility, RNN poses significant challenges due to their complex internal structures, which impede the effective use of model parallelism. This often leads to a reliance on data parallelism to accelerate RNN performance. Furthermore, RNN demands extensive computational resources due to their large parameter counts. This doctoral research proposes innovative High-Performance Computing (HPC) strategies to optimize RNN deployment on CPUs, enhancing their efficiency in resource-limited settings. Through algorithmic improvements and memory-efficient techniques, this work seeks to maximize the potential of parallel computing for RNN, thereby transforming AI parallel system landscapes.This thesis introduces "Wavefront-Parallelization" (W-Par), which integrates model parallelism into unidirectional RNN to enhance inference and training on CPUs. W-Par utilizes fine-grained pipeline parallelism through wavefront computations, which are particularly effective for multi-layer RNNs on multi-core CPUs. These techniques allow for efficient workload distribution across parallel tasks while managing the dependencies of each RNN cell. Empirical results show that W-Par significantly outperforms existing implementations, achieving speed-ups of up to 6.6x times on contemporary multi-core CPU architectures, and maintains robust performance across various core and memory configurations without requiring source code modifications.Additionally, the thesis presents "Bidirectional-Parallelization" (B-Par), a novel execution model for Bidirectional Recurrent Neural Networks (BRNN). B-Par leverages inherent data and control dependencies in forward and reverse-order RNN in BRNN, dividing workloads efficiently across parallel tasks without needing layer-specific synchronization barriers. Tests on the TIDIGITS speech database and Wikipedia dataset demonstrate that B-Par significantly exceeds the performance of leading frameworks like TensorFlow-Keras and PyTorch, with speed-ups of up to 2.34x and 9.16x times, respectively, while maintaining accuracy.Finally, this thesis introduces the "Semi-Bidirectional RNN" (SB-RNN), a novel architecture that synergistically integrates the strengths of both unidirectional and bidirectional RNN. SB-RNN maintains the parameter count of unidirectional RNN while incorporating backward connections across layers to enhance the capability for information retention. This architecture enables SB-RNN to match and potentially exceed the accuracy of unidirectional RNN and bidirectional RNN (BRNN) across both CPU and GPU environments. Specifically, on the sentiment analysis task of the Stanford Sentiment Treebank (SST) dataset, SB-RNN demonstrates superior performance with 56.61% fewer parameters than their unidirectional counterparts, leading to a significant reduction in training time by 52.94%.Overall, this thesis introduces three advanced techniques: W-Par, B-Par, and SB-RNN - that significantly improve the efficiency and performance of RNN and BRNN models on multi-core CPUs and GPUs, facilitating enhanced processing across various applications without extensive code alterations.

Committee:
     PRESIDENT: BEIVIDE PALACIO, JULIO RAMON
     SECRETARI: BARRADO MUXI, CRISTINA
     VOCAL NO PRESENCIAL: REDDI, VIJAY JANAPA
Thesis abstract: The emergence of new applications such as autonomous machines (e.g., robots or self-driving cars) and XR (Extended Reality) promises to revolutionize how society interacts with technology in the rapidly advancing digital era. These technologies, deployed on edge devices, often rely on mobile or embedded SoCs (Systems-on-a-Chip) operating CV (Continuous Vision) pipelines that periodically capture and analyze environmental light.A typical CV SoC comprises two main components: a frontend for image capture and a backend for processing vision algorithms. The frontend usually includes an off-chip camera sensor and an ISP (Image Signal Processor), which processes the pixel stream, converting raw sensor data into high-quality images. The backend—comprising components such as the CPU, GPU, or specialized accelerators—analyzes the images stored in the main memory's framebuffer to extract perception insights and enable advanced decision-making.Existing research identifies visual localization, object detection, and tracking as the primary bottlenecks in these emerging applications. Those algorithms face two principal challenges when deployed in mobile CV systems: latency and energy consumption. For example, an XR headset uses visual localization to track head motion for accurate frame rendering, where latency can cause discomfort. In self-driving cars, localization ensures centimeter-level precision, with delays compromising safety, especially at higher speeds. Additionally, high energy consumption limits the operation of battery-powered mobile systems.This thesis embarks on a strategic journey to elevate mobile CV systems' performance and energy efficiency through several key contributions:We begin by analyzing a state-of-the-art visual localization engine on a CPU. The localization engine processes camera images, extracting and tracking features to estimate camera pose. Our evaluations reveal feature extraction as the primary bottleneck, accounting for 60% to 90% of total localization latency.Next, we investigate highly specialized hardware accelerator designs for image processing. The first contribution is LOCATOR (Low-power ORB Accelerator for Autonomous Cars), a hardware accelerator designed for ORB (Oriented FAST and Rotated BRIEF) feature extraction. LOCATOR processes image tiles with two parallel pipelines for feature detection and description, employing techniques like optimal static bank access patterns, caching mechanisms, and selective port replication. These optimizations yield a 16.8× speedup for ORB feature extraction, 1.9× end-to-end speedup, and 2.1× energy reduction per frame compared to a baseline mobile CPU.Realizing the need for more programmable and versatile solutions, our second contribution, SLIDEX (Sliding Window Extension for Image Processing), introduces a domain-specific vector ISA extension for CPUs. SLIDEX exploits the sliding window processing model, interpreting vector registers as overlapping windows to maximize data-level parallelism. SLIDEX reduces data access and movement, enhancing tasks like 2D convolutions and stencil operations, resulting in a 1.2× speedup and up to 19% energy reduction.The third contribution, δLTA (δon't Look Twice, It's Alright), decouples camera frame sampling from backend processing. δLTA allows the frontend to identify and skip redundant image regions, focusing processing only on significant changes. δLTA reduces unnecessary memory accesses and redundant computations, lowering localization tail and average latency by 7.2% and 15.2%, respectively, and energy consumption by 17%.Finally, IRIS (Image Region ISP-Software Prioritization) repurposes computations performed by the frontend ISP, segmenting and prioritizing image regions based on detail and motion. IRIS allows the backend to process relevant regions first, reducing latency and energy consumption by up to 9% in tail latency, 20% in average latency, and 16% in energy savings without additional overhead.

Committee:
     PRESIDENT: MARTINEZ RIVERA, RICARDO VICTOR
     SECRETARI: CASTILLO REYES, OCTAVIO
     VOCAL NO PRESENCIAL: HERNÁNDEZ GUTIERREZ, JOSÉ ALBERTO
Thesis abstract: Future radio access network (RAN) will operate with massive and heterogeneous small-cell deployments and end-to-end (e2e) connectivity in support of diverse beyond fifth-generation (B5G) use cases. More and more connectivity services are requiring not only stringent but also more predictable Quality of Service (QoS) performance, measured in terms of key performance indicators (KPI) such as throughput and capacity. With the advent of Open RAN (O-RAN), the implementation of flexible function splits/placement for guaranteeing target latency requirements and improved reliability is enabled. This smart operation must also precisely match capacity requirements, which typically reduces energy consumption, by managing the number of active base stations (BS) that are required to support user traffic requirements.In addition to RAN, access and metro optical networks play a fundamental role to meet e2e requirements, in terms of both capacity and latency. Thus, optical transport networks can operate autonomously, e.g., to adapt optical capacity to current traffic. Nevertheless, the foreseen B5G scenarios poses challenges to autonomous optical network operation, since smart RAN operation generates highly variable and unpredictable traffic. Indeed, smart operation of both RAN and fixed network makes difficult to achieve optimal e2e connectivity performance if they are done independently. Instead, both domains can share knowledge and coordinate with the objective of guaranteeing strict QoS requirements and efficient resource utilization of e2e connectivity services.This Ph.D. thesis is dedicated to developing solutions that coordinate both smart and autonomous operation of RAN and fixed optical network segments under B5G foreseen scenarios. To this aim, three goals are defined. The first goal aims at providing a methodology for smart operation of RAN cells with dense deployment of BSs, which is one of the most challenging scenarios envisioned for B5G networks. Relying on Open-RAN capabilities regarding monitoring and control loops, an AI-based approach that integrates both supervised and unsupervised machine learning algorithms to achieve intelligent RAN operation is proposed. The objective is to minimize energy consumption by switching on/off BSs while providing the desired coverage and required capacity needs.From the previous contributions and lessons learnt, the second goal focuses on analyzing the impact in terms of traffic to be supported by the underlying access and metro optical networks assuming smart RAN operation. The main conclusion of this goal is that smart RAN operation can have a critical affectation on underlying optical transport, which requires coordination between RAN and optical networks for efficient e2e network management.In light of the above, the third goal tackles two different use cases where coordination between smart RAN operation and autonomous optical network management provide benefits and allow e2e QoS assurance. On the one hand, a procedure for which RAN configuration changes to be performed are anticipated to the fixed network controller is proposed. By means of contextual data, fixed access and metro traffic prediction models are extended with RAN context in order to predict ongoing sharp traffic changes. On the other hand, a second use case focuses in the scenario of serving particular services where a maximum e2e delay need to be assured. In particular, a dynamic coordination mechanism is proposed, where actual RAN delay is informed in case that this exceeds a given level, so that the fixed network controller can adapt its budget and take decisions according to the new constraint.The research leading to these results has received funding from the Smart Networks and Services Joint Undertaking under the European Union's Horizon Europe research and innovation programme under Grant Agreement No. 101096120 (SEASON), and the MICINN IBON (PID2020-114135RB-I00) projects and from the ICREA Institution.

Committee:
     PRESIDENT: TERBOVEN, CHRISTIAN
     SECRETARI: LABARTA MANCHO, JESUS JOSE
     VOCAL: MARONGIU, ANDREA
Thesis abstract: The task execution model is widely used in computer engineering, it helps developers to design, develop and understand software systems. OpenMP is the de-facto programming model to parallelize sequential algorithms on shared-memory machines. Coupled with the task parallelization, OpenMP is able to conveniently parallelize structured and non-structured applications, it also allows users to offload work onto accelerators as target tasks. However, the runtime overhead incurred by the OpenMP tasking model is an important concern for users to develop OpenMP task programs. This work focuses on improving OpenMP tasking model.Firstly, we carried out an analysis of the performance overhead and bottleneck of mainstream task implementations and proposed a solution in the OpenMP specification to tackle it. To elaborate, we observe that a significant portion of the overhead in the tasking model stems from thread contention, where multiple threads compete to access shared resources simultaneously, such as task queues, causing these threads to stall. As the number of cores in modern architectures increases, this further hampers the scalability of OpenMP tasking. We propose a mechanism that creates graphs representing sets of OpenMP tasks. Once built, executing such graphs incurs less runtime overhead by drastically reducing the access to shared resources. This mechanism is exposed to the users as a new OpenMP directive, namely Taskgraph.Secondly, we implemented the proposed solution, the taskgraph directive, in both GCC (prototype implementation) and LLVM compilers (complete implementation). Initially, our focus was on the GCC compiler, particularly its runtime system: libgomp. Our prototype implementation in this compiler demonstrated promising performance improvement using taskgraph. However, it also revealed a performance bottleneck in libgomp: all tasks are scheduled into a common queue, leading to significant contention and resulting in poor performance and scalability compared to LLVM.The complete implementation of the taskgraph framework is in the LLVM compiler. Our modifications in the compiler range from the front-end to the middle-end of the compiler, in addition to its runtime library: libomp. This framework allows users to declare taskgraph directives in OpenMP C/C++ code to create graphs conveniently, at either compile time or run-time. The experiments show that the taskgraph framework outperforms the original task implementations from GCC and LLVM. We carried out the experiments on nodes of the Marenostrum4 supercomputer.Finally, we enhance the OpenMP offloading mechanism by leveraging taskgraph. Particularly, we implemented the transformation of taskgraph to CUDA graphs. Consequently, our framework enhances the interoperability of OpenMP with other programming models (in this case, CUDA) and improves the performance of OpenMP accelerator model by alleviating the synchronization overhead.With these contributions, this thesis ameliorates both the OpenMP tasking and accelerator models. The framework has been used by other Ph.D. students to develop their research, for example, Cyril Cetre from Thales Research and Technology successfully improved the performance of a cyber-physical application by utilizing static generation of CUDA graphs, as presented in this manuscript. Furthermore, the OpenMP Language Committee accepted our proposition to include the taskgraph directive into the OpenMP Specification v6.0. This thesis also contributed to the upstream LLVM repository. These commits are mainly focused on the record-and-replay mechanism of taskgraph, serving also as a basis for the official taskgraph implementation in the LLVM. We hope with these endeavors, this work will promote the use of OpenMP task in general.