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Computer Architecture

The doctoral programme in Computer Architecture is delivered by the UPC’s Department of Computer Architecture. The main aim of the programme, which has a long track record, is to produce researchers with capabilities of the highest international standard in the subject areas it covers; namely, computer architecture, operating systems, communications and computer networks. 

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COORDINATOR

Masip Bruin, Xavier

CONTACT

Doctoral Unit - ICT North Campus Management and Support Unit (UTGCNTIC). C. Jordi Girona, 1-3. Building B4-003 (North Campus)
Tel.: 934 054 198
E-mail: doctorat.ac@upc.edu

Programme website

General information

Access profile

The doctoral programme focuses primarily on computer architecture. Applicants must therefore hold a master's degree in an area that covers this field (i.e. computer sciences). The appropriateness of a student’s qualifications will be determined based on the academic curriculum vitae they submit when applying for admission.

As a general rule, to be admitted to the doctoral programme offered by the Department of Computer Architecture, applicants should have completed a bachelor's degree, preferably in informatics or telecommunications, and a master's degree in one of these areas, such as the master's degree in Innovation and Research in Informatics (MIRI) in any of its specialisations. Applicants must also have a high level of English proficiency and be willing to join a working group, participate in research projects, travel and undertake periods of mobility abroad, and interact with colleagues outside the UPC (staff of companies and research centres, members of other groups, etc.).

Output profile

Doctoral candidates who complete a doctoral degree will have acquired the following competencies, which are needed to carry out quality research (Royal Decree 99/2011, of 28 January, which regulates official doctoral studies):

a) A systematic understanding of the field of study and a mastery of the research skills and methods related to the field.
b) An ability to conceive, design or create, put into practice and adopt a substantial process of research or creation.
c) An ability to contribute to pushing back the frontiers of knowledge through original research.
d) A capacity for critical analysis and an ability to assess and summarise new and complex ideas.
e) An ability to communicate with the academic and scientific community and with society in general as regards their fields of knowledge in the manner and languages that are typical of the international scientific community to which they belong.
f) An ability to foster scientific, technological, social, artistic and cultural progress in academic and professional contexts within a knowledge-based society.

The award of a doctoral degree must equip the graduate for work in a variety of settings, especially those requiring creativity and innovation. Doctoral graduates must have at least acquired the personal skills needed to:

a) Develop in contexts in which there is little specific information.
b) Find the key questions that must be answered to solve a complex problem.
c) Design, create, develop and undertake original, innovative projects in their field.
d) Work as part of a team and independently in an international or multidisciplinary context.
e) Integrate knowledge, deal with complexity and make judgements with limited information.
f) Offer criticism on and intellectually defend solutions.

Finally, with respect to competencies, doctoral students must:

a) have acquired advanced knowledge at the frontier of their discipline and demonstrated, in the context of internationally recognised scientific research, a deep, detailed and well-grounded understanding of theoretical and practical issues and scientific methodology in one or more research fields;
b) have made an original and significant contribution to scientific research in their field of expertise that has been recognised as such by the international scientific community;
c) have demonstrated that they are capable of designing a research project that serves as a framework for carrying out a critical analysis and assessment of imprecise situations, in which they are able to apply their contributions, expertise and working method to synthesise new and complex ideas that yield a deeper knowledge of the research context in which they work;
d) have developed sufficient autonomy to set up, manage and lead innovative research teams and projects and scientific collaborations (both national and international) within their subject area, in multidisciplinary contexts and, where appropriate, with a substantial element of knowledge transfer;
e) have demonstrated that they are able to carry out their research activity in a socially responsible manner and with scientific integrity;
f) have demonstrated that they are able to participate in scientific discussions at the international level in their field of expertise and disseminate the results of their research activity to audiences of all kinds;
g) have demonstrated, within their specific scientific context, that they are able to make cultural, social or technological advances and promote innovation in all areas within a knowledge-based society.

Number of places

40

Duration of studies and dedication regime

Duration
The maximum period of study for full-time doctoral studies is three years, counted from the date of admission to the programme to the date of submission of the doctoral thesis. The academic committee of the doctoral programme may authorise a doctoral candidate to pursue doctoral studies on a part-time basis. In this case, the maximum period of study is five years, counting from the date of admission to the programme to the date of submission of the doctoral thesis. For calculating these periods, the date of admission is considered to be the date of the first enrolment for tutorials, and the date of submission the moment in which the Doctoral School officially deposits the doctoral thesis.

For full-time doctoral candidates, the minimum period of study is two years, counted from the date of an applicant's admission to the programme until the date on which the doctoral thesis is deposited; for part-time doctoral candidates it is four years. When there are justified grounds for doing so, and the thesis supervisor and academic tutor have given their authorisation, doctoral candidates may request that the academic committee of their doctoral programme exempt them from the minimum period of study requirement.

The calculation of periods of study will not include periods of absence due to illness, pregnancy or any other reason provided for in the regulations in force. Students who find themselves in any of these circumstances must notify the academic committee of the doctoral programme, which, where appropriate, must inform the Doctoral School. Doctoral candidates may also temporarily withdraw from the programme for up to one year, and this period may be extended for an additional year. Doctoral candidates who wish to interrupt their studies must submit a justified request to the academic committee of the doctoral programme, which will decide whether or not to approve the request. Each programme will establish conditions for readmission to doctoral studies.

Extension
If full-time doctoral candidates have not applied to deposit their thesis by the end of the three-year period of study, the academic committee of the programme may authorise an extension of up to one year. In exceptional circumstances, a further one-year extension may be granted, subject to the conditions established by the corresponding doctoral programme. In the case of part-time doctoral candidates, an extension of two years may be authorised. In both cases, in exceptional circumstances a further one-year extension may be granted by the Doctoral School's Standing Committee, upon the submission of a reasoned application by the academic committee of the doctoral programme.

Dismissal from the doctoral programme
A doctoral candidate may be dismissed from a doctoral programme for the following reasons:

  • The doctoral candidate submitting a justified application to withdraw from the programme.
  • The maximum period of study and of extensions thereof ending.
  • The doctoral candidate not having enrolled every academic year (unless he or she has been authorised to temporarily withdraw).
  • The doctoral candidate failing two consecutive assessments.
  • The doctoral candidate having disciplinary proceedings filed against him or her that rule that he or she must be dismissed from the UPC.

Dismissal from the programme implies that doctoral candidates cannot continue studying at the UPC and the closing of their academic record. This notwithstanding, they may apply to the academic committee of the programme for readmission and the committee must reevaluate them in accordance with the criteria established in the regulations.

Enrollment aid


Organization

COORDINATOR:
ACADEMIC COMMISSION OF THE PROGRAM:
Other Universities:



STRUCTURAL UNITS:
  • Department of Computer Architecture (PROMOTORA)
Specific URL of the doctoral program:
http://www.ac.upc.edu/ca/docencia/doctorat/programa-de-doctorat-arquitectura-de-computadors

CONTACT:

Doctoral Unit - ICT North Campus Management and Support Unit (UTGCNTIC). C. Jordi Girona, 1-3. Building B4-003 (North Campus)
Tel.: 934 054 198
E-mail: doctorat.ac@upc.edu


Agreements with other institutions

BSC (Barcelona Supercomputing Center)

Access, admission and registration

Access profile

The doctoral programme focuses primarily on computer architecture. Applicants must therefore hold a master's degree in an area that covers this field (i.e. computer sciences). The appropriateness of a student’s qualifications will be determined based on the academic curriculum vitae they submit when applying for admission.

As a general rule, to be admitted to the doctoral programme offered by the Department of Computer Architecture, applicants should have completed a bachelor's degree, preferably in informatics or telecommunications, and a master's degree in one of these areas, such as the master's degree in Innovation and Research in Informatics (MIRI) in any of its specialisations. Applicants must also have a high level of English proficiency and be willing to join a working group, participate in research projects, travel and undertake periods of mobility abroad, and interact with colleagues outside the UPC (staff of companies and research centres, members of other groups, etc.).

Access requirements

Applicants must hold a Spanish bachelor’s degree or equivalent and a Spanish master’s degree or equivalent, provided they have completed a minimum of 300 ECTS credits on the two degrees (Royal Decree 43/2015, of 2 February)

In addition, the following may apply:

  • Holders of an official degree awarded by a university in Spain or any other country in the European Higher Education Area, pursuant to the provisions of Article 16 of Royal Decree 1393/2007, of 29 October, which establishes official university course regulations, who have completed a minimum of 300 ECTS credits on official university degrees, of which at least 60 must be at the master's degree level.
  • Holders of an official Spanish bachelor’s degree comprising at least 300 credits, as provided for by EU regulations. Holder of degrees of this kind must complete bridging courses unless the curriculum of the bachelor’s degree in question included research training credits equivalent in value to those which would be earned on a master's degree.
  • Holders of an official university qualification who, having passed the entrance examination for specialised medical training, have completed at least two years of a training course leading to an official degree in a health-sciences specialisation.
  • Holders of a degree issued under a foreign education system. In these cases, homologation is not required, but the UPC must verify that the degree certifies a level of training equivalent to an official Spanish master's degree and qualifies the holder for admission to doctoral studies in the country where it was issued. Admission on this basis does not imply homologation of the foreign degree or its recognition for any purpose other than admission to doctoral studies.
  • Holders of a Spanish doctoral qualification issued under previous university regulations.
  • Note 1: Doctoral studies entrance regulations for holders of an undergraduate degree awarded before the introduction of the EHEA (CG 47/02 2014)

    Note 2: Governing Council Decision 64/2014, which approves the procedure and criteria for assessing the fulfilment of academic admission requirements for doctoral studies by holders of non-homologated foreign degrees (CG 25/03 2014)

Admission criteria and merits assessment

Given the highly heterogeneous academic environment, to ensure that applicants have an appropriate background, the programme has modified its internal admission procedure. Admission requirements are now grouped in two categories: formal and conceptual. If an applicant does not meet the formal conditions, the conceptual requirements are not considered.

Formal analysis (FA)

Applicants must meet the requirements established in the administrative regulations for programme. The focus here is on ensuring that applicants have the level of studies and the number of credits required. Applicants who do not meet these requirements will not be admitted to the programme.

Conceptual analysis (CA)

This includes points related to the applicant’s level of knowledge and capabilities. Another factor taken into account is whether there is a research group interested in the work the applicant wishes to undertake. In this section, the following requirements apply:

• ED: An engineering degree related to the subject area of the programme, preferably in informatics or telecommunications. In exceptional cases, students with other qualifications, such as a degree in mathematics or a master's degree in computer science, may also be admitted.

• RG: Whether or not the applicant has the support of a research group linked to the programme and a supervisor/tutor to complete their doctoral thesis.

• BA: Experience or explicit knowledge of computer architecture; acquired, for example, by completing a master’s thesis in this area, collaborating with a group working in the field, etc.

• EN: Proficiency in English, certified by an internationally accepted testing system (TOEFL, etc.).

• FU: Availability of funding for the student’s research, whether through the institution where they completed their previous studies or through the group in which the thesis work would be carried out.

All of these factors will be taken into account by applying the following formula:
Admission: FA*(0.1ED + 0.4RG + 0.1BA + 0.2EN + 0.2FU)

Training complements

To ensure that students admitted to the programme have the knowledge they need to make good progress, the academic committee of the doctoral programme may require that they pass specific bridging courses. Additional training requirements will be determined based on each student's academic background. In such cases, the committee will keep track of the bridging courses completed and establish appropriate criteria to limit their duration. Bridging courses may provide research or cross-disciplinary training, but in no case may doctoral students be required to enrol for 60 or more ECTS credits. Taking into account the doctoral student activity report, the academic committee may propose measures that complement those specified in the regulations and which result in doctoral students who do not meet the specified requirements being excluded from the programme.

Therefore, the organisers of the doctoral programme may admit students on the condition that they complete specific bridging courses to fill gaps identified in their academic background and ensure that they have the knowledge needed to successfully complete their doctoral studies. The number of bridging courses required will depend on each student's background and may require the completion of 18 or 30 additional ECTS credits. The following considerations will apply: 

• Credits for additional training will correspond to three or five master's level subjects, selected from among master’s degrees linked to the doctoral programme. 

• The academic committee will decide how many credits a student must take by reviewing the subjects they took to earn their entrance qualification in order to identify possible gaps in their knowledge. A range of factors are taken into account to determine what subjects a student must take. Apart from subject names, other points considered include the number of hours of study completed for each subject, the topics covered, and even the university where the subjects were taken. The syllabus for each subject will be reviewed, with particular attention to the number of hours allocated in the syllabus. 

• The specific subjects to be taken will be determined by the academic committee in agreement with the student's tutor. Subjects will be selected with the aim of achieving two key goals: i) increasing the student’s knowledge in areas where gaps have been identified; ii) increasing their knowledge in the area of their doctoral thesis.

Enrolment period for new doctoral students

Students enrolling in the doctoral programme for the first time must do so by the deadline specified in the admission decision.
Unless otherwise expressly indicated, enrolments corresponding to admission decisions issued from the second half of April on must be completed within the ordinary enrolment period for the current academic year. 

More information at the registration section for new doctoral students

Enrolment period

Ordinary period for second and successive enrolments: first half of October.

More information at the general registration section

Monitoring and evaluation of the doctoral student

Procedure for the preparation and defense of the research plan

Doctoral candidates must submit a research plan, which will be included in their doctoral student activity report, before the end of the first year. The plan may be improved over the course of the doctoral degree. It must be endorsed by the tutor and the supervisor, and it must include the method that is to be followed and the aims of the research.

At least one of these annual assessments will include a public presentation and defence of the research plan and work done before a committee composed of three doctoral degree holders, which will be conducted in the manner determined by each academic committee. The examination committee awards a Pass or Fail mark. A Pass mark is a prerequisite for continuing on the doctoral programme. Doctoral candidates awarded a Fail mark must submit a new research plan for assessment by the academic committee of the doctoral programme within six months.

The committee assesses the research plan every year, in addition to all of the other activities in the doctoral student activity report. Doctoral candidates who are awarded two consecutive Fail marks for the research plan will be obliged to definitely withdraw from the programme.

If they change the subject of their thesis, they must submit a new research plan.

Formation activities

Tutorial hours are considered highly important for training students and monitoring their progress. Time spent on tutorials is estimated as follows:

Activity: Tutorial.

Hours: 2 hours/week × 48 weeks of class × 3 years = 288 hours. 

Type: compulsory

In weekly tutorials, students will discuss their work and the progress they are making with their tutor. Tutors may provide students with guidance based on the results obtained and anticipated progress with the aim of facilitating achievement of objectives that have been set. During the hours allocated for these sessions, tutors may also talk to students about research groups that are working in areas closely related to the topic of their thesis and that may be interested in engaging with the work to be carried out by the student, or that it may be worthwhile for the student to contact to discuss possible collaborations. Tutorials may also include internal meetings with other members of the research group to discuss issues of common interest in relation to the research being conducted.

This activity will continue throughout the time that it takes a student to complete their doctoral thesis (estimated at three years).

Procedure for assignment of tutor and thesis director

The academic committee of the doctoral programme assigns a thesis supervisor to each doctoral candidate when they are admitted or enrol for the first time, taking account of the thesis supervision commitment referred to in the admission decision.

The thesis supervisor will ensure that training activities carried out by the doctoral candidate are coherent and suitable, and that the topic of the candidate’s doctoral thesis will have an impact and make a novel contribution to knowledge in the relevant field. The thesis supervisor will also guide the doctoral candidate in planning the thesis and, if necessary, tailoring it to any other projects or activities undertaken. The thesis supervisor will generally be a UPC professor or researcher who holds a doctoral degree and has documented research experience. This includes PhD-holding staff at associated schools (as determined by the Governing Council) and UPC-affiliated research institutes (in accordance with corresponding collaboration and affiliation agreements). When thesis supervisors are UPC staff members, they also act as the doctoral candidate’s tutor.

PhD holders who do not meet these criteria (as a result of their contractual relationship or the nature of the institution to which they are attached) must be approved by the UPC Doctoral School's Standing Committee in order to participate in a doctoral programme as researchers with documented research experience.

The academic committee of the doctoral programme may approve the appointment of a PhD-holding expert who is not a UPC staff member as a candidate’s thesis supervisor. In such cases, the prior authorisation of the UPC Doctoral School's Standing Committee is required. A UPC staff member who holds a doctoral degree and has documented research experience must also be proposed to act as a co-supervisor, or as the doctoral candidate’s tutor if one has not been assigned.

A thesis supervisor may step down from this role if there are justified reasons (recognised as valid by the committee) for doing so. If this occurs, the academic committee of the doctoral programme will assign the doctoral candidate a new thesis supervisor.

Provided there are justified reasons for doing so, and after hearing any relevant input from the doctoral candidate, the academic committee of the doctoral programme may assign a new thesis supervisor at any time during the period of doctoral study.

If there are academic reasons for doing so (an interdisciplinary topic, joint or international programmes, etc.) and the academic committee of the programme gives its approval, an additional thesis supervisor may be assigned. Supervisors and co-supervisors have the same responsibilities and academic recognition.

The maximum number of supervisors of a doctoral thesis is two: a supervisor and a co-supervisor.

For theses carried out under a cotutelle agreement or as part of an Industrial Doctorate, if necessary and if the agreement foresees it this maximum number of supervisors may not apply. This notwithstanding, the maximum number of supervisors belonging to the UPC is two.

More information at the PhD theses section

Permanence

The academic committee of the programme may authorise an extension of up to one year for full-time doctoral candidates who have not applied to deposit their thesis by the end of the three-year period of study, in the terms outlined in the Academic Regulations for Doctoral Studies of the Universitat Politècnica de Catalunya. In the case of part-time candidates, an extension of two years may be authorised. In both cases, in exceptional circumstances a further one-year extension may be granted by the Doctoral School's Standing Committee, upon the submission of a reasoned application by the academic committee of the doctoral programme.

A doctoral candidate may be dismissed from a doctoral programme for the following reasons:

  • The doctoral candidate submitting a justified application to withdraw from the programme.
  • The maximum period of study and of extensions thereof ending.
  • The doctoral candidate not having enrolled every academic year (unless he or she has been authorised to temporarily withdraw).
  • The doctoral candidate failing two consecutive assessments.
  • The doctoral candidate having disciplinary proceedings filed against him or her that rule that he or she must be dismissed from the UPC.

Dismissal from the programme implies that doctoral candidates cannot continue studying at the UPC and the closing of their academic record. This notwithstanding, they may apply to the academic committee of the programme for readmission and the committee must reevaluate them in accordance with the criteria established in the regulations.

International Mention

The doctoral degree certificate may include International Doctorate mention. In this case, the doctoral candidate must meet the following requirements:

a) During the period of study leading to the award of the doctoral degree, the doctoral candidate must have spent at least three months at a respected higher education institution or research centre outside Spain to complete courses or do research work. The stays and activities carried out must be endorsed by the thesis supervisor and authorised by the academic committee of the programme. The candidate must provide a certifying document issued by the person responsible for the research group of the body or bodies where the stay or activity was completed. This information will be added to the doctoral student’s activity report.
b) Part of the thesis (at least the summary and conclusions) must be written and presented in one of the languages commonly used for science communication in the relevant field of knowledge, which must not be an official language of Spain. This rule does not apply to stays and reports in Spanish or to experts from Spanish-speaking countries.
c) At least two PhD-holding experts belonging to a higher education institution or research centre outside Spain must have issued officially certified reports on the thesis.
d) The thesis examination committee must have included at least one PhD-holding expert from a higher education or research institution outside Spain who was not responsible for the candidate’s stay abroad (point a) above).
e) The thesis defence must have taken place on UPC premises or, in the case of joint programmes, at the location specified in the collaboration agreement.

Learning resources

The programme has access to the resources of the research groups of the Department of Computer Architecture and research centres associated with the programme, as well as institutional resources made available by the UPC. Specifically, students have access to:

1) Resources of the following research centres associated with the programme:

• BSC: Barcelona Supercomputing Center, http://www.bsc.es 

• Advanced Broadband Communications Centre (CCABA), http://www.ccaba.upc.edu 

• Aeronautical and Space Science Research Centre (CRAE)https://recerca.upc.edu/crae/

2) Resources of research groups and laboratories associated with the programme:

• ANA/CRAAX:  http://research.ac.upc.edu/ana 

• ARCO:  http://research.ac.upc.edu/ARCO

• CAP:  http://research.ac.upc.edu/CAP/hpc

- CBA: http://research.ac.upc.edu/cba

• CNDS:  http://research.ac.upc.edu/cnds

• DAMA-UPC: http:// research.ac.upc.edu/dama

• DMAG: http://research.ac.upc.edu/dmag

• ICARUS: http://www.icarus.upc.edu/

Doctoral Theses

List of authorized thesis for defense

  • BARZEGAR, SIMA: Autonomous and reliable operation of multilayer optical networks
    Author: BARZEGAR, SIMA
    Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Article-based thesis
    Deposit date: 25/04/2022
    Reading date: 03/06/2022
    Reading time: 11:00
    Reading place: FIB Sala d'Actes Martí Recober - B6 - FIB UPC Campus nord
    Thesis director: VELASCO ESTEBAN, LUIS DOMINGO | RUIZ RAMÍREZ, MARC
    Committee:
         PRESIDENT: SHARIATI, MOHAMMAD BEHNAM
         SECRETARI: JUNYENT GIRALT, GABRIEL
         VOCAL: CASTRO CASALES, ALBERTO ANDRÉS
    Thesis abstract: This Ph.D. thesis focuses on the reliable autonomous operation of multilayer optical networks.The first objective focuses on the reliability of the optical network and proposes methods for health analysis related to Quality of Transmission (QoT) degradation. Such degradation is produced by soft-failures in optical devices and fibers in core and metro segments of the operators¿ transport networks. Here, we compare estimated and measured QoT in the optical transponder by using a QoT tool based on GNPy. We show that the changes in the values of input parameters of the QoT model representing optical devices can explain the deviations and degradation in performance of such devices. We use reverse engineering to estimate the value of those parameters that explain the observed QoT. We show by simulation a large anticipation in soft-failure detection, localization and identification of degradation before affecting the network. Finally, for validating our approach, we experimentally observe the high accuracy in the estimation of the modeling parameters.The second objective focuses on multilayer optical networks, where lightpaths are used to connect packet nodes thus creating virtual links (vLink). Specifically, we study how lightpaths can be managed to provide enough capacity to the packet layer without detrimental effects in their Quality of Service (QoS), like added delays or packet losses, and at the same time minimize energy consumption. Such management must be as autonomous as possible to minimize human intervention. We study the autonomous operation of optical connections based on digital subcarrier multiplexing (DSCM). We propose several solutions for the autonomous operation of DSCM systems. In particular, the combination of two modules running in the optical node and in the optical transponder activate and deactivate subcarriers to adapt the capacity of the optical connection to the upper layer packet traffic. The module running in the optical node is part of our Intent-based Networking (IBN) solution and implements prediction to anticipate traffic changes. Our comprehensive study demonstrates the feasibility of DSCM autonomous operation and shows large cost savings in terms of energy consumption. In addition, our study provides a guideline to help vendors and operators to adopt the proposed solutions.The final objective targets at automating packet layer connections (PkC). Automating the capacity required by PkCs can bring further cost reduction to network operators, as it can limit the resources used at the optical layer. However, such automation requires careful design to avoid any QoS degradation, which would impact Service Level Agreement (SLA) in the case that the packet flow is related to some customer connection. We study autonomous packet flow capacity management. We apply RL techniques and propose a management lifecycle consisting of three different phases: 1) a self-tuned threshold-based approach for setting up the connection until enough data is collected, which enables understanding the traffic characteristics; 2) RL operation based on models pre-trained with generic traffic profiles; and 3) RL operation based on models trained with the observed traffic. We show that RL algorithms provide poor performance until they learn optimal policies, as well as when the traffic characteristics change over time. The proposed lifecycle provides remarkable performance from the starting of the connection and it shows the robustness while facing changes in traffic. The contribution is twofold: 1) and on the one hand, we propose a solution based on RL, which shows superior performance with respect to the solution based on prediction; and 2) because vLinks support packet connections, coordination between the intents of both layers is proposed. In this case, the actions taken by the individual PkCs are used by the vLink intent. The results show noticeable performance compared to independent vLink operation.
  • GOMEZ CRESPO, CONSTANTINO: On the co-design of scientific applications and long vector architectures
    Author: GOMEZ CRESPO, CONSTANTINO
    Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Deposit date: 06/04/2022
    Reading date: 23/05/2022
    Reading time: 11:00
    Reading place: FIB- Sala E106 ¿ Edif. C6 - FIB https://rediris.zoom.us/j/85152355615?pwd=9EjhFixtfA9nMjjC_I983OYfvV8p-h.1
    Thesis director: MANTOVANI, FILIPPO | CASAS GUIX, MARC
    Committee:
         PRESIDENT: SUAREZ GARCIA, MARIA ESTELA
         SECRETARI: PALOMAR PÉREZ, OSCAR
         VOCAL NO PRESENCIAL: JIMBOREAN, ALEXANDRA
    Thesis abstract: The landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. To improve the efficiency of next-generation compute devices, architects are looking for solutions beyond the commodity CPU approach. In 2021, the five most powerful supercomputers in the world use either GP-GPU (General-purpose computing on graphics processing units) accelerators or a customized CPU specially designed to target HPC applications. This trend is only expected to grow in the next years motivated by the compute demands of science and industry.As architectures evolve, the ecosystem of tools and applications must follow. The choices in the number of cores in a socket, the floating point-units per core and the bandwidth through the memory hierarchy among others, have a large impact in the power consumption and compute capabilities of the devices. To balance CPU and accelerators, designers require accurate tools for analyzing and predicting the impact of new architectural features on the performance of complex scientific applications at scale. In such a large design space, capturing and modeling with simulators the complex interactions between the system software andhardware components is a defying challenge. Moreover, applications must be able to exploit those designs with aggressive compute capabilities and memory bandwidth configurations. Algorithms and data structures will need to be redesigned accordingly to expose a high degree of data-level parallelism allowing them to scale in large systems. Therefore, next-generation computing devices will be the result of a co-design effort in hardware and applications supported by advanced simulation tools. In this thesis, we focus our work on the co-design of scientific applications and long vector architectures. We significantly extend a multi-scale simulation toolchain enabling accurate performance and power estimations of large-scale HPC systems. Through simulation, we explore the large design space in current HPC trends over a wide range of applications.We extract speedup and energy consumption figures analyzing the trade-offs and optimal configurations for each of the applications. We describe in detail the optimization process of two challenging applications on real vector accelerators, achieving outstanding operation performance and full memory bandwidth utilization. Overall, we provide evidence-basedarchitectural and programming recommendations that will serve as hardware and software co-design guidelines for the next generation of specialized compute devices.
  • MACIÀ SORROSAL, SANDRA: Towards a domain specific language for computational fluid dynamics in HPC
    Author: MACIÀ SORROSAL, SANDRA
    Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Temporary seizure
    Deposit date: 08/04/2022
    Reading date: 26/05/2022
    Reading time: 11:00
    Reading place: FIB - ( meet.google.com/cmi-giqz-dyh ) Sala BSC-Edifici Repsol , Planta 1 ¿ Auditori ¿ FIB
    Thesis director: AYGUADÉ PARRA, EDUARD | BELTRAN QUEROL, VICENÇ
    Committee:
         PRESIDENT: QUINTANA ORTI, ENRIQUE SALVADOR
         SECRETARI: MARTORELL BOFILL, XAVIER
         VOCAL NO PRESENCIAL: BULL, JONATHAN MARK
    Thesis abstract: High-Performance Computing (HPC) evolves vertiginously.Supercomputers are increasingly powerful and complex machines that require deep expertise to be well-exploited.Currently, scientists develop HPC codes using General Purpose Languages (GPLs) and parallel programming models.However, such abstractions are falling short; developing advanced numerical methods and cutting-edge parallelisation strategies requires time, effort and deep computer science expertise, which is unreasonable to expect from other domain scientists.Scientific productivity has become a research challenge.In order to overcome this challenge, computational science demands instruments for practical parallel computations, abstracting scientists from HPC complexities while ensuring the efficient and full exploitation of HPC systems.In this context, Domain-Specific Languages (DSLs) are promising frameworks integrating specific knowledge and capable of automating parts of the code development process.DSLs can become the so-needed productive working environment by decoupling the problem description from the algorithmic implementation.Our task is to push the boundaries of DSLs capabilities and explore their strengths and limitations in HPC environments.We focus on the Computational Fluid Dynamics (CFD) domain to accomplish it.CFD is a field of vast scientific interest and essential for many branches of engineering and industry. Besides its broad applicability, results are obtained from numerical approximations, which can be highly accurate in a reasonable amount of time and investments if CFD codes exploit HPC resources.The object of this thesis is the design and development of Saiph, a DSL for CFD in HPC, exploring the limits of usability, numerical abstraction and automated high-per\-for\-mance.This research provides a high-productivity tool allowing for the direct transcription of CFD problems to generate optimised and mathematically checked code.Saiph provides suitable high-order numerical methods delivering competitive performance and highly accurate and stable results on the numerical side.Moreover, Saiph automatically combines numerical methods, freeing the users from numerical complexities.Finally, the automated use of parallelisation strategies provides high efficient and scalable parallel codes, exploiting current HPC machines at different resource levels.Vectorisation and data-blocking techniques automatically combine with shared and distributed memory parallelisms through fork-join or task-based models and domain decomposition techniques, respectively.We demonstrate the viability and benefits of the DSL, proving it to be a productive and competitive tool for the scientific community.Hence, the DSL philosophy arises as a promising research methodology facing the Exascale era.
  • PEREDO ANDRADE, OSCAR FRANCISCO: Large scale geostatistics with locally varying anisotropy
    Author: PEREDO ANDRADE, OSCAR FRANCISCO
    Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Deposit date: 11/04/2022
    Reading date: pending
    Reading time: pending
    Reading place: pending
    Thesis director: HERRERO ZARAGOZA, JOSE RAMON
    Committee:
         PRESIDENT: QUINTANA ORTI, ENRIQUE SALVADOR
         SECRETARI: AYGUADÉ PARRA, EDUARD
         VOCAL NO PRESENCIAL: ALIAGA ESTELLÉS, JOSE IGNACIO
    Thesis abstract: Classical geostatistical methods are based on the hypothesis of stationarity, which allows to apply repetitive sampling in different locations of the spatial domain, in order to obtain enough information to infer cumulative distributions. In case of non stationarity, anisotropy is observed in the underlying physical phenomena. This feature manifest itself as preferential directions of continuity in the phenomena, i.e. properties are more continuous in one orientation than in another. In the case of local anisotropy, each location of the domain in study presents different preferential directions of continuity. The locally varying anisotropy (LVA) approach in geostatistics allows to incorporate a field of local anisotropy parameters defined for each domain point. With this additional input, more realistic spatial simulations can be generated, including geological features to the computational model such as folds, veins, faults, among others. Since the seminal article published by Boisvert and Deutsch (2011), to the best of the author's knowledge, no further analysis or public code improvements were developed. This is in part because acceleration and parallelization techniques must be applied to the inner kernels of the baseline LVA codes. Large execution time is needed to generate small-scale domain simulations, making large-scale domain simulations a prohibitive task.The contributions of this thesis are accelerating and parallelizing classical and LVA-based geostatistical simulation methods, particularly sequential simulation, which is one of the most common and computationally intensive methods in the field. This fact was recently remarked by some of the main authors in the field, Gómez-Hernández and Srivastava (2021), which shows the relevance of this work today. Two main parallel algorithms and an optimized version of a kd-tree search implementation are presented, all of them applied to both classical and LVA-based sequential simulation implementations. The first parallel algorithm is related to the parallel simulation of different domain points, after rearranging the order of simulation but preserving the exact results of a single-thread execution. The second parallel algorithm is related to the parallel search of neighbour points in the domain, which will be used to build data dependencies for the parallel simulation of points. The optimized kd-tree search was used in each test case in order to reduce the computational complexity of neighbour search tasks. Its modified implementation reduces the number of branching instructions and introduces specialized code sections to accelerate the execution. The main focus is on multi-core architectures using OpenMP and optimization techniques applied to Fortran and C++ codes.Additionally, acceleration and parallelization techniques were also applied to auxiliary applications, such as shortest path and variogram calculation on hybrid CPU/GPU architectures using Fortran, C++ and CUDA codes. In the last application, an analytical and heuristic model was developed to estimate the optimal workload distribution between CPU and GPU in the hybrid context.The overall results of this work are a set of applications that will allow researchers and practitioners to accelerate dramatically the execution of their experiments and simulations, being sgsim, sisim, sgs-lva and sisim-lva the accelerated codes presented. Final speedup results of 11x and 50x are obtained for non-LVA codes using 16 threads, and 56x and 1822x are obtained for LVA codes using 20 threads. These tools can be combined with other geostatistical tools, in order to improve the existing landscape of open source codes that can be used in practical scenarios.
  • TABATABAEIMEHR, FATEMEHSADAT: Distributed collaborative knowledge management for optical network
    Author: TABATABAEIMEHR, FATEMEHSADAT
    Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Deposit date: 26/04/2022
    Reading date: 02/06/2022
    Reading time: 16:00
    Reading place: FIB- Sala d'actes Martí Recober. Edifici B6 Campus Nord
    Thesis director: VELASCO ESTEBAN, LUIS DOMINGO | COMELLAS COLOME, JAUME
    Committee:
         PRESIDENT: SHARIATI, MOHAMMAD BEHNAM
         SECRETARI: CAREGLIO, DAVIDE
         VOCAL: CASTRO CASALES, ALBERTO ANDRÉS
    Thesis abstract: Network automation has been long time envisioned. In fact, the Telecommunications Management Network (TMN), defined by the International Telecommunication Union (ITU), is a hierarchy of management layers (network element, network, service, and business management), where high-level operational goals propagate from upper to lower layers.The network management architecture has evolved with the development of the Software Defined Networking (SDN) concept that brings programmability to simplify configuration (it breaks down high-level service abstraction into lower-level device abstractions), orchestrates operation, and automatically reacts to changes or events. Besides, the development and deployment of solutions based on Artificial Intelligence (AI) and Machine Learning (ML) for making decisions (control loop) based on the collected monitoring data enables network automation, which targets at reducing operational costs. AI/ML approaches usually require large datasets for training purposes, which are difficult to obtain. The lack of data can be compensated with a collective self-learning approach. In this thesis, we go beyond the aforementioned traditional control loop to achieve an efficient knowledge management (KM) process that enhances network intelligence while bringing down complexity.In this PhD thesis, we propose a general architecture to support KM process based on four main pillars, which enable creating, sharing, assimilating and using knowledge. Next, two alternative strategies based on model inaccuracies and combining model are proposed. To highlight the capacity of KM to adapt to different applications, two use cases are considered to implement KM in a purely centralized and distributed optical network architecture. Along with them, various policies are considered for evaluating KM in data- and model- based strategies. The results target to minimize the amount of data that need to be shared and reduce the convergence error. We apply KM to multilayer networks and propose the PILOT methodology for modeling connectivity services in a sandbox domain. PILOT uses active probes deployed in Central Offices (COs) to obtain real measurements that are used to tune a simulation scenario reproducing the real deployment with high accuracy. A simulator is eventually used to generate large amounts of realistic synthetic data for ML training and validation.We apply KM process also to a more complex network system that consists of several domains, where intra-domain controllers assist a broker plane in estimating accurate inter-domain delay. In addition, the broker identifies and corrects intra-domain model inaccuracies, as well as it computes an accurate compound model. Such models can be used for quality of service (QoS) and accurate end-to-end delay estimations.Finally, we investigate the application on KM in the context of Intent-based Networking (IBN). Knowledge in terms of traffic model and/or traffic perturbation is transferred among agents in a hierarchical architecture. This architecture can support autonomous network operation, like capacity management.It shall be mentioned that part of the work reported in this thesis has been done within the framework of European and National projects. Specifically, the H2020 METRO-HAUL and B5G-OPEN funded by the European Commission, and the MINECO TWINS and AEI IBON, both funded by the Spanish Ministry of Economy, Industry and Competitiveness.

Last update: 20/05/2022 04:45:19.

List of lodged theses

No hi ha registres per mostrar.

Last update: 20/05/2022 04:30:19.

List of defended theses by year

  • BENEDICTE ILLESCAS, PEDRO: Smart hardware designs for probabilistically-analyzable processor architectures
    Author: BENEDICTE ILLESCAS, PEDRO
    Thesis link: http://hdl.handle.net/10803/674151
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Reading date: 07/04/2022
    Thesis director: CAZORLA ALMEIDA, FRANCISCO JAVIER | LABARTA MANCHO, JESUS JOSE

    Committee:
         PRESIDENT: PÉREZ CERROLAZA, JUAN MARTIN
         SECRETARI: MORETÓ PLANAS, MIQUEL
         VOCAL NO PRESENCIAL: JALLE IBARRA, JAVIER
    Thesis abstract: Future Critical Real-Time Embedded Systems (CRTES), like those is planes, cars or trains, require more and more guaranteed performance in order to satisfy the increasing performance demands of advanced complex software features. While increased performance can be achieved by deploying processor techniques currently used in High-Performance Computing (HPC) and mainstream domains, their use challenges the software timing analysis, a necessary step in CRTES' verification and validation. Cache memories are known to have high impact in performance, and in fact, current CRTES include multicores usually with several levels of cache. In this line, this Thesis aims at increasing the guaranteed performance of CRTES by using techniques for caches building upon time randomization and providing probabilistic guarantees of tasks' execution time.In this Thesis, we first focus on on improving cache placement and replacement to improve guaranteed performance. For placement, different existing policies are explored in a multi-level cache setup, and a solution is reached in which different of those policies are combined. For cache replacement, we analyze a pathological scenario that no cache policy so far accounts and propose several policies that fix this pathological scenario.For shared caches in multicore we observe that contention is mainly caused by private writes that go through to the shared cache, yet using a pure write-back policy also has its drawbacks. We propose a hybrid approach to mitigate this contention. Building on this solution, the next contribution tackles a problem caused by the need of some reliability mechanisms in CRTES. Implementing reliability close to the processor's core has a significant impact in performance. A look-ahead error detection solution is proposed to greatly mitigate the performance impact.The next contribution proposes the first hardware prefetcher for CRTES with arbitrary cache hierarchies. Given its speculative nature, prefetchers that have a guaranteed positive impact on performance are difficult to design. We present a framework that provides execution time guarantees and obtains a performance benefit.Finally, we focus on the impact of timing anomalies in CRTES with caches. For the first time, a definition and taxonomy of timing anomalies is given for Measurement-Based Timing Analysis. Then, we focus on a specific timing anomaly that can happen with caches and provide a solution to account for it in the execution time estimates.

  • ELSHAZLY, HATEM MOHAMED ABDELFATTAH EID: Programming model abstractions for optimizing I/O intensive applications
    Author: ELSHAZLY, HATEM MOHAMED ABDELFATTAH EID
    Thesis link: http://hdl.handle.net/10803/673638
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Reading date: 28/01/2022
    Thesis director: BADIA SALA, ROSA MARIA

    Committee:
         PRESIDENT: JEANNOT, EMMANUEL
         SECRETARI: CORTÉS ROSSELLÓ, ANTONIO
         VOCAL NO PRESENCIAL: CARRETERO PÉREZ, JESÚS
    Thesis abstract: This thesis contributes from the perspective of task-based programming models to the efforts of optimizing I/O intensive applications. Throughout this thesis, we propose programming model abstractions and mechanisms that target a twofold objective: from the one hand, improve the I/O and total performance of applications on nowadays complex storageinfrastructures. From the other hand, achieve such performance improvement without increasing the complexity of applicationsprogramming. The following paragraphs briefly summarize each of our contributions.First, towards exploiting compute-I/O patterns of I/O intensive applications and transparently improving I/O and total performance, we propose a number of abstractions that we refer to as I/O Awareness abstractions. An I/O aware task-based programming model is able to separate the handling of I/O and computations by supporting I/O Tasks. The execution of suchtasks can overlap with compute tasks execution. Moreover, we provide programming model support to improve I/O performance by addressing the issue of I/O congestion. This is achieved by using Storage Bandwidth Constraints to control the level of taskparallelism. We support two types of such constraints: (i) Static storage bandwidth constraints that are manually set by applicationdevelopers. (ii) Auto-tunable constraints that are automatically set and tuned throughout the execution of application.Second, in order to exploit the heterogeneity of modern storage systems to improve performance in a transparent manner, we propose a set of capabilities that we refer to as Storage heterogeneity Awareness. A storage-heterogeneity aware task-based programming model builds on the concepts and abstractions that are introduced in the first contribution to improve the I/O performance of applications on heterogeneous storage systems. More specifically, such programming models support thefollowing features: (i) abstracting the heterogeneity of the storage devices and exposing them as one hierarchical storage resource. (ii) supporting dedicated I/O scheduling. (iii) Finally, we introduce a mechanism that automatically and periodicallyflushes obsolete data from higher storage layers to lower storage layers.Third, targeting increasing parallelism levels of applications, we propose a Hybrid Programming Model that combines task-based programming models and MPI. In this programming model, tasks are used to achieve coarse-grained parallelism on large-scale distributed infrastructures, whereas MPI is used to gain fine-grained parallelism by parallelizing tasks execution. Such a hybridprogramming model offers the possibility to enable parallel I/O and high-level I/O libraries in tasks. We enable such a hybrid programming model by supporting Native MPI Tasks. These tasks are native to the programming model for two reasons: they execute task code as opposed to calling external MPI binaries or scripts. Also, the data transfers and input/output handling is done in a completely transparent manner to application developers. Therefore, increasing parallelism levels while easing the design and programming of applications.Finally, to exploit the inherent parallelism opportunities in applications and overlap computation with I/O, we propose an Eager mechanism for releasing data dependencies. Unlike the traditional approach for releasing dependencies, eagerly releasing datadependencies allows successor tasks to be released for execution as soon as their data dependencies are ready, without having to wait for predecessor task(s) to completely finish execution. In order to support the eager-release of data dependencies, we describe the following core modifications to the design of task-based programming models: (i) defining and managing datadependency relationships as parameter-aware dependencies (ii) a mechanism for notifying the programming model that an output data has been generated before the execution of the producer task ends.

  • RAMÍREZ LAZO, CRISTÓBAL: Adaptable register file organization for vector processors
    Author: RAMÍREZ LAZO, CRISTÓBAL
    Thesis link: http://hdl.handle.net/10803/674224
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Reading date: 04/04/2022
    Thesis director: CRISTAL KESTELMAN, ADRIAN | RAMÍREZ SALINAS, MARCO ANTONIO

    Committee:
         PRESIDENT: WEISER, URI
         SECRETARI: ARMEJACH SANOSA, ADRIÀ
         VOCAL: RATKOVIC, IVAN
    Thesis abstract: Today there are two main vector processors design trends. On the one hand, we have vector processors designed for long vectors lengths such as the SX-Aurora TSUBASA which implements vector lengths of 256 elements (16384-bits). On the other hand, we have vector processors designed for short vectors such as the Fujitsu A64FX that implements vector lengths of 8 elements (512-bit) ARM SVE. However, short vector designs are the most widely adopted in modern chips. This is because, to achieve high-performance with a very high-efficiency, applications executed on long vector designs must feature abundant DLP, then limiting the range of applications. On the contrary, short vector designs are compatible with a larger range of applications. In fact, in the beginnings, long vector length implementations were focused on the HPC market, while short vector length implementations were conceived to improve performance in multimedia tasks. However, those short vector length extensions have evolved to better fit the needs of modern applications. In that sense, we believe that this compatibility with a large range of applications featuring high, medium and low DLP is one of the main reasons behind the trend of building parallel machines with short vectors. Short vector designs are area efficient and are "compatible" with applications having long vectors; however, these short vector architectures are not as efficient as longer vector designs when executing high DLP code. In this thesis, we propose a novel vector architecture that combines the area and resource efficiency characterizing short vector processors with the ability to handle large DLP applications, as allowed in long vector architectures. In this context, we present AVA, an Adaptable Vector Architecture designed for short vectors (MVL = 16 elements), capable of reconfiguring the MVL when executing applications with abundant DLP, achieving performance comparable to designs for long vectors. The design is based on three complementary concepts. First, a two-stage renaming unit based on a new type of registers termed as Virtual Vector Registers (VVRs), which are an intermediate mapping between the conventional logical and the physical and memory registers. In the first stage, logical registers are renamed to VVRs, while in the second stage, VVRs are renamed to physical registers. Second, a two-level VRF, that supports 64 VVRs whose MVL can be configured from 16 to 128 elements. The first level corresponds to the VVRs mapped in the physical registers held in the 8KB Physical Vector Register File (P-VRF), while the second level represents the VVRs mapped in memory registers held in the Memory Vector Register File (M-VRF). While the baseline configuration (MVL=16 elements) holds all the VVRs in the P-VRF, larger MVL configurations hold a subset of the total VVRs in the P-VRF, and map the remaining part in the M-VRF. Third, we propose a novel two-stage vector issue unit. In the first stage, the second level of mapping between the VVRs and physical registers is performed, while issuing to execute is managed in the second stage.This thesis also presents a set of tools for designing and evaluating vector architectures. First, a parameterizable vector architecture model implemented on the gem5 simulator to evaluate novel ideas on vector architectures. Second, a Vector Architecture model implemented on the McPAT framework to evaluate power and area metrics. Finally, the RiVEC benchmark suite, a collection of ten vectorized applications from different domains focusing on benchmarking vector microarchitectures.

  • RASOL, KURDMAN ABDULRAHMAN RASOL: Flexible architecture for the future internet scalability of SDN control plane
    Author: RASOL, KURDMAN ABDULRAHMAN RASOL
    Thesis link: http://hdl.handle.net/10803/673562
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Reading date: 28/01/2022
    Thesis director: DOMINGO PASCUAL, JORDI

    Committee:
         PRESIDENT: MANZONI, PIETRO
         SECRETARI: PERELLO MUNTAN, JORDI
         VOCAL NO PRESENCIAL: MARZO LAZARO, JOSE LUIS
    Thesis abstract: Software-Defined Networking (SDN) separates the control plane from the data plane. The initial SDN approach involves a single centralized controller, which may not scale properly as a network grows in size. Distributed controllers have emerged to address the disadvantages of a single centralized controller. The control architecture needs to be distributed with traffic control between switches and controllers and among the controllers in order to allow SDNs for several thousand switches. One of the most significant research challenges for distributed controller architectures is to effectively manage controllers, which includes allocating enough controllers to appropriate network locations. To address these daunting issues, we make the following major contributions:This thesis expands the method of solving the Control Placement Problem (CPP) based on the K-means and K-center algorithms to include a Hierarchical Controller Placement Problem (HCPP), located at a high level of Super Controller (SC), a middle level of Master Controllers (MCs), and the lowest level of domain controllers (DCs). The optimization metric addresses latency between the controller and the switches assigned to it.. The proposed architecture and methodology are implemented using the topology of Western European NRENs from the Internet Topology Zoo. The entire network topology is divided into clusters, and the optimal number of controllers (DCs) and their placement are determined for each cluster. MC placement optimization determines the optimal number of MCs and their optimal placement. As a second contribution, an accumulated latency is defined to solve CPP, which takes into account both the latency between the controller and its associated switches and the latency between controllers. Under the constraint of latency, an optimization problem is formulated as per mixed-integer linear programming (MILP). The goal of the research is to reduce accumulated latency while also reducing the number of network controllers and optimizing their placement to achieve an optimal balance. The performance of the developed method is evaluated on Internet2 OS3E real network topology. To achieve the third objective, a metric was developed that includes reliability. The communication latency between controllers should also be considered because a low controller-switch delay does not always imply a short controller-controller delay for a particular controller placement. As the third contribution, we propose a novel metric for CPP to improve the reliability of controllers that takes into account both communication latency and communication reliability between switches and controllers, as well as between controllers. When a single link fails, reliability is taken into account. This aspect concluded by identifying the optimal controller placement to achieve low latencies in control plane traffic. The goal of this project is to reduce the average latency. As the fourth contribution, this study evaluates the Joint Latency and Reliability-aware Controller Placement (LRCP) optimization model. As the evaluation metric, control plane latency (CPL) is defined as the sum of the average switch-to-controller latency and average inter-controller latency. The latency of the control plane, utilizing the actual latencies of the real network topology, is calculated for every optimum placement in the network. In the case of a failure of the single link, the actual CPL for LRCP placements is calculated and evaluated to determine how good LRCP placements are. CPL metrics are used to compare latency and reliability metrics with other models. This study provides proof that the developed methodologies for large-scale networks are highly powerful in terms of searching for all feasible controller placements while assessing the outcomes. In addition, compared to previous work including latency among controllers and reliability for an event of single-link failure.

  • SANCHEZ VERDEJO, ROMMEL: HPC memory systems: Implications of system simulation and checkpointing
    Author: SANCHEZ VERDEJO, ROMMEL
    Thesis link: http://hdl.handle.net/10803/673620
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Reading date: 04/02/2022
    Thesis director: RADOJKOVIC, PETAR

    Committee:
         PRESIDENT: MARAZAKIS, EMMANOUIL (MANOLIS)
         SECRETARI: MARTORELL BOFILL, XAVIER
         VOCAL NO PRESENCIAL: ZIVANOVIC, DARKO
    Thesis abstract: The memory system is a significant contributor for most of the current challenges in computer architecture: application performance bottlenecks and operational costs in large data-centers as HPC supercomputers. With the advent of emerging memory technologies, the exploration for novel designs on the memory hierarchy for HPC systems is an open invitation for computer architecture researchers to improve and optimize current designs and deployments. System simulation is the preferred approach to perform architectural explorations due to the low cost to prototype hardware systems, acceptable performance estimates, and accurate energy consumption predictions. Despite the broad presence and extensive usage of system simulators, their validation is not standardized; either because the main purpose of the simulator is not meant to mimic real hardware, or because the design assumptions are too narrow on a particular computer architecture topic. This thesis provides the first steps for a systematic methodology to validate system simulators when compared to real systems. We unveil real-machine´s micro-architectural parameters through a set of specially crafted micro-benchmarks. The unveiled parameters are used to upgrade the simulation infrastructure in order to obtain higher accuracy in the simulation domain. To evaluate the accuracy on the simulation domain, we propose the retirement factor, an extension to a well-known application´s performance methodology. Our proposal provides a new metric to measure the impact simulator´s parameter-tuning when looking for the most accurate configuration. We further present the delay queue, a modification to the memory controller that imposes a configurable delay for all memory transactions that reach the main memory devices; evaluated using the retirement factor, the delay queue allows us to identify the sources of deviations between the simulator infrastructure and the real system. Memory accesses directly affect application performance, both in the real-world machine as well as in the simulation accuracy. From single-read access to a unique memory location up to simultaneous read/write operations to a single or multiple memory locations, HPC applications memory usage differs from workload to workload. A property that allows to glimpse on the application´s memory usage is the workload´s memory footprint. In this work, we found a link between HPC workload´s memory footprint and simulation performance. Actual trends on HPC data-center memory deployments and current HPC application¿s memory footprint led us to envision an opportunity for emerging memory technologies to include them as part of the reliability support on HPC systems. Emerging memory technologies such as 3D-stacked DRAM are getting deployed in current HPC systems but in limited quantities in comparison with standard DRAM storage making them suitable to use for low memory footprint HPC applications. We exploit and evaluate this characteristic enabling a Checkpoint-Restart library to support a heterogeneous memory system deployed with an emerging memory technology. Our implementation imposes negligible overhead while offering a simple interface to allocate, manage, and migrate data sets between heterogeneous memory systems. Moreover, we showed that the usage of an emerging memory technology it is not a direct solution to performance bottlenecks; correct data placement and crafted code implementation are critical when comes to obtain the best computing performance. Overall, this thesis provides a technique for validating main memory system simulators when integrated in a simulation infrastructure and compared to real systems. In addition, we explored a link between the workload´s memory footprint and simulation performance on current HPC workloads. Finally, we enabled low memory footprint HPC applications with resilience support while transparently profiting from the usage of emerging memory deployments.

  • SÁNCHEZ BARRERA, ISAAC: Exploiting data locality in cache-coherent NUMA systems
    Author: SÁNCHEZ BARRERA, ISAAC
    Thesis link: http://hdl.handle.net/10803/674228
    Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
    Department: (DAC)
    Mode: Normal
    Reading date: 06/04/2022
    Thesis director: CASAS GUIX, MARC | MORETÓ PLANAS, MIQUEL

    Committee:
         PRESIDENT: SCHULZ, MARTIN
         SECRETARI: CANAL CORRETGER, RAMON
         VOCAL NO PRESENCIAL: BUTTARI, ALFREDO
    Thesis abstract: The end of Dennard scaling has caused a stagnation of the clock frequency in computers.To overcome this issue, in the last two decades vendors have been integrating larger numbers of processing elements in the systems, interconnecting many nodes, including multiple chips in the nodes and increasing the number of cores in each chip. The speed of main memory has not evolved at the same rate as processors, it is much slower and there is a need to provide more total bandwidth to the processors, especially with the increase in the number of cores and chips.Still keeping a shared address space, where all processors can access the whole memory, solutions have come by integrating more memories: by using newer technologies like high-bandwidth memories (HBM) and non-volatile memories (NVM), by giving groups cores (like sockets, for example) faster access to some subset of the DRAM, or by combining many of these solutions. This has caused some heterogeneity in the access speed to main memory, depending on the CPU requesting access to a memory address and the actual physical location of that address, causing non-uniform memory access (NUMA) behaviours.Moreover, many of these systems are cache-coherent (ccNUMA), meaning that changes in the memory done from one CPU must be visible by the other CPUs and transparent for the programmer.These NUMA behaviours reduce the performance of applications and can pose a challenge to the programmers. To tackle this issue, this thesis proposes solutions, at the software and hardware levels, to improve the data locality in NUMA systems and, therefore, the performance of applications in these computer systems.The first contribution shows how considering hardware prefetching simultaneously with thread and data placement in NUMA systems can find configurations with better performance than considering these aspects separately. The performance results combined with performance counters are then used to build a performance model to predict, both offline and online, the best configuration for new applications not in the model. The evaluation is done using two different high performance NUMA systems, and the performance counters collected in one machine are used to predict the best configurations in the other machine.The second contribution builds on the idea that prefetching can have a strong effect in NUMA systems and proposes aNUMA-aware hardware prefetching scheme. This scheme is generic and can be applied to multiple hardware prefetchers with a low hardware cost but giving very good results. The evaluation is done using a cycle-accurate architectural simulator and provides detailed results of the performance, the data transfer reduction and the energy costs.Finally, the third and last contribution consists in scheduling algorithms for task-based programming models. These programming models help improve the programmability of applications in parallel systems and also provide useful information to the underlying runtime system. This information is used to build a task dependency graph (TDG), a directed acyclic graph that models the application where the nodes are sequential pieces of code known as tasks and the edges are the data dependencies between the different tasks. The proposed scheduling algorithms use graph partitioning techniques and provide a scheduling for the tasks in the TDG that minimises the data transfers between the different NUMA regions of the system. The results have been evaluated in real ccNUMA systems with multiple NUMA regions.

Last update: 19/05/2022 05:01:04.

Theses related publications

AUTHOR:BENEDICTE ILLESCAS, PEDRO
Title:Smart hardware designs for probabilistically-analyzable processor architectures
Reading date:07/04/2022
Director:CAZORLA ALMEIDA, FRANCISCO JAVIER
Co-director:LABARTA MANCHO, JESUS JOSE
Mention:No mention
RELATED PUBLICATIONS
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Modelling the confidence of timing analysis for time randomised caches
11th IEEE International Symposium on Industrial Embedded Systems
Presentation date: 05/2016
Presentation of work at congresses

RPR: a random replacement policy with limited pathological replacements
33th ACM Symposium On Applied Computing
Presentation date: 09/04/2018
Presentation of work at congresses

Design and integration of hierarchical-placement multi-level caches for real-Time systems
2018 Design, Automation and Test in Europe Conference and Exhibition
Presentation date: 23/04/2018
Presentation of work at congresses

HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems
30th Euromicro Conference on Real-Time Systems
Presentation date: 01/06/2018
Presentation of work at congresses

Towards limiting the impact of timing anomalies in complex real-time processors
24th Asia and South Pacific Design Automation Conference
Presentation date: 01/2019
Presentation of work at congresses

LAEC: Look-Ahead Error Correction codes in embedded processors L1 data cache
22nd Design, Automation and Test in Europe Conference and Exhibition
Presentation date: 03/2019
Presentation of work at congresses

Performance analysis and optimization of automotive GPUs
31st International Symposium on Computer Architecture and High Performance Computing
Presentation date: 16/10/2019
Presentation of work at congresses

Modeling contention interference in crossbar-based systems via Sequence-Aware Pairing (SeAP)
IEEE Real-Time and Embedded Technology and Applications Symposium
Presentation date: 04/2020
Presentation of work at congresses

SafeTI: a hardware traffic injector for MPSoC functional and timing validation
27th IEEE International Symposium on On-Line Testing and Robust System Design
Presentation date: 06/2021
Presentation of work at congresses

AUTHOR:SÁNCHEZ BARRERA, ISAAC
Title:Exploiting data locality in cache-coherent NUMA systems
Reading date:06/04/2022
Director:CASAS GUIX, MARC
Co-director:MORETÓ PLANAS, MIQUEL
Mention:International Mention
RELATED PUBLICATIONS
POSTER: Graph partitioning applied to dag scheduling to reduce NUMA effects
PPoPP '18 - 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Presentation date: 24/02/2018
Presentation of work at congresses

Reducing data movement on large shared memory systems by exploiting computation dependencies
32nd International Conference on Supercomputing
Presentation date: 12/06/2018
Presentation of work at congresses

On the benefits of tasking with OpenMP
International Workshop on OpenMP
Presentation date: 13/09/2019
Presentation of work at congresses

Modeling and optimizing NUMA effects and prefetching with machine learning
34th International Conference on Supercomputing
Presentation date: 06/2020
Presentation of work at congresses

AUTHOR:RAMÍREZ LAZO, CRISTÓBAL
Title:Adaptable register file organization for vector processors
Reading date:04/04/2022
Director:CRISTAL KESTELMAN, ADRIAN
Co-director:RAMÍREZ SALINAS, MARCO ANTONIO
Mention:International Mention
RELATED PUBLICATIONS
A RISC-V simulator and benchmark suite for designing and evaluating vector architectures
Ramírez, C.; Hernández, C.; Palomar, Ó.; Unsal, O.; Ramirez, M.; Cristal, A.
ACM transactions on architecture and code optimization, ISSN: 1544-3566 (JCR Impact Factor-2020: 0.919; Quartil: Q4)
Publication date: 11/2020
Journal article

An academic RISC-V silicon implementation based on open-source components
XXXV Conference on Design of Circuits and Integrated Systems
Presentation date: 20/11/2020
Presentation of work at congresses

BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge
27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
Presentation date: 28/02/2022
Presentation of work at congresses

BiSon-e: A Lightweight and High-Performance Accelerator for Narrow Integer Linear Algebra Computing on the Edge
27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
Presentation of work at congresses

Adaptable Register File Organization for Vector Processors
28th IEEE International Symposium on High-Performance Computer Architecture
Presentation date: 02/04/2022
Presentation of work at congresses

AUTHOR:SANCHEZ VERDEJO, ROMMEL
Title:HPC memory systems: Implications of system simulation and checkpointing
Reading date:04/02/2022
Tutor/a:AYGUADÉ PARRA, EDUARD
Director:RADOJKOVIC, PETAR
Mention:No mention
RELATED PUBLICATIONS
PROFET: modeling system performance and energy without simulating the CPU
Radulovic, M.; Sanchez, R.; Carpenter, P.; Radojkovic, Petar; Jacob, B.; Ayguade, E.
Proceedings of the ACM on Measurement and Analysis of Computing Systems, ISSN:
Publication date: 06/2019
Journal article

Performance and power estimation of STT-MRAM main memory with reliable system-level simulation
Asifuzzaman, K.; Sanchez, R.; Radojkovic, Petar
ACM transactions on embedded computing systems, ISSN: 1558-3465 (JCR Impact Factor-2020: 1.193; Quartil: Q4)
Publication date: 01/2022
Journal article

Microbenchmarks for detailed validation and tuning of hardware simulators
15th International Conference on High Performance Computing & Simulation
Presentation date: 20/07/2017
Presentation of work at congresses

Main memory latency simulation: the missing link
International Symposium on Memory Systems 2018
Presentation date: 01/10/2018
Presentation of work at congresses

Rethinking cycle accurate DRAM simulation
International Symposium on Memory Systems
Presentation date: 09/2019
Presentation of work at congresses

AUTHOR:RASOL, KURDMAN ABDULRAHMAN RASOL
Title:Flexible architecture for the future internet scalability of SDN control plane
Reading date:28/01/2022
Director:DOMINGO PASCUAL, JORDI
Mention:No mention
RELATED PUBLICATIONS
Joint placement latency optimization of the control plane
7th International Symposium on Networks, Computers and Communications
Presentation date: 20/10/2020
Presentation of work at congresses

Joint latency and reliability-aware controller placement
35th International Conference on Information Networking
Presentation date: 10/01/2021
Presentation of work at congresses

Multi-level hierarchical controller placement in software defined networking
12th International Networking Conference
Presentation date: 21/09/2020
Presentation of work at congresses

AUTHOR:ELSHAZLY, HATEM MOHAMED ABDELFATTAH EID
Title:Programming model abstractions for optimizing I/O intensive applications
Reading date:28/01/2022
Director:BADIA SALA, ROSA MARIA
Mention:No mention
RELATED PUBLICATIONS
Accelerated execution via eager-release of dependencies in task-based workflows
Elshazly, H.; Lordan, F.; Ejarque, J.; Badia, R.M.
The international journal of high performance computing applications (IJHPCA), ISSN: 1094-3420 (JCR Impact Factor-2019: 3.1
Publication date: 01/07/2021
Journal article

Towards enabling I/O awareness in task-based programming models
Elshazly, H.; Ejarque, J.; Lordan, F.; Badia, R.M.
Future generation computer systems, ISSN: 0167-739X (JCR Impact Factor-2019: 10.2
Publication date: 08/2021
Journal article

Performance meets programmability: Enabling native Python MPI tasks in PyCOMPSs
28th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
Presentation date: 03/2020
Presentation of work at congresses

AUTHOR:PUEYO CENTELLES, ROGER
Title:Towards LoRa mesh networks for the IoT
Reading date:12/11/2021
Director:MESEGUER PALLARES, ROQUE
Co-director:FREITAG, FELIX
Mention:No mention
RELATED PUBLICATIONS
LoRaMoto: a communication system to provide safety awareness among civilians after an earthquake
Roger Pueyo Centelles; Meseguer, R.; Freitag, F.; Navarro, L.; Ochoa, Sergio F.; Santos, R.
Future generation computer systems, ISSN: 0167-739X (JCR Impact Factor-2019: 6.125; Quartil: Q1)
Publication date: 02/2021
Journal article

An IoT-based infrastructure to enhance self-evacuations in natural hazardous events
Finochietto, M.; Micheletto, M.; Eggly, G.; Roger Pueyo Centelles; Santos, R.; Ochoa, Sergio F.; Meseguer, R.; Orozco, J.
Personal and ubiquitous computing, ISSN: 1617-4909 (JCR Impact Factor-2019: 2.0; Quartil: Q3)
Publication date: 05/02/2021
Journal article

Beyond the star of stars: An introduction to multihop and mesh for LoRa and LoRaWAN
Roger Pueyo Centelles; Freitag, F.; Meseguer, R.; Navarro, L.
IEEE pervasive computing, ISSN: 1536-1268 (JCR Impact Factor-2019: 4.418; Quartil: Q1)
Publication date: 04/2021
Journal article

On-Device Training of Machine Learning Models on Microcontrollers with Federated Learning
Monfort Grau, M.; Roger Pueyo Centelles; Freitag, F.
Electronics (Switzerland), ISSN: 2079-9292 (JCR Impact Factor-2020: 2.7
Publication date: 14/02/2022
Journal article

A LoRa-Based communication system for coordinated response in an earthquake Aftermath
13th International Conference on Ubiquitous Computing and Ambient Intelligence
Presentation date: 2019
Presentation of work at congresses

REDEMON: Resilient Decentralized Monitoring system for edge Infrastructures
20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing
Presentation date: 05/2020
Presentation of work at congresses

DIMON: Distributed Monitoring System for decentralized edge clouds in Guifi.net
12th IEEE Conference on Service-Oriented Computing and Applications
Presentation date: 2019
Presentation of work at congresses

End user-managed service deployments in microclouds at the network edge
8th IEEE Global Conference on Consumer Electronics
Presentation date: 10/2019
Presentation of work at congresses

A monitoring system for distributed edge infrastructures with decentralized coordination
5th International Symposium on Algorithmic Aspects of Cloud Computing
Presentation date: 09/2019
Presentation of work at congresses

On-device training of machine learning models on microcontrollers with a look at federated learning
GoodIT 2021 - 1st ACM International Conference on Information Technology for Social Good
Presentation date: 09/2021
Presentation of work at congresses

AUTHOR:BARANDA HORTIGÜELA, JORGE
Title:End-to-end network service orchestration in heterogeneous domains for next-generation mobile networks
Reading date:09/11/2021
Tutor/a:CABELLOS APARICIO, ALBERTO
Director:MANGUES BAFALLUY, JOSEP
Mention:No mention
RELATED PUBLICATIONS
Orchestration of end-to-end network services in the 5G-Crosshaul multi-domain multi-technology transport network
Baranda, J.; Josep Mangues-Bafalluy; Pascual, I.; José Núñez-Martínez
IEEE communications magazine, ISSN: 0163-6804 (JCR Impact Factor-2018: 10.356; Quartil: Q1)
Publication date: 07/2018
Journal article

Realising the network service federation vision: enabling automated multidomain orchestration of network services
Baranda, J.; Josep Mangues-Bafalluy; Martínez, R.
IEEE Vehicular technology magazine: connecting the Mobile world, ISSN: 1556-6072 (JCR Impact Factor-2020: 10.384; Quartil: Q1)
Publication date: 06/2020
Journal article

Automating Vertical Services Deployments over the 5GT Platform
Li, X.; Deiss, T.; Mangues-Bafalluy, J.; Baranda, J.; Costa, X.; Landi, G.; Bernardos, C.; Iovanna, P.; Zurita, A.; Bertin, P.
IEEE communications magazine, ISSN: 0163-6804 (JCR Impact Factor-2020: 9.619; Quartil: Q1)
Publication date: 07/2020
Journal article

Automated Service Provisioning and Hierarchical SLA Management in 5G Systems
Li, X.; Chiasserini, C.F.; Josep Mangues-Bafalluy; Baranda, J.; Landi, G.; Martini, B.; Costa, X.; Puligheddu, C.; Valcarenghi, L.
IEEE transactions on network and service management, ISSN: 1932-4537 (JCR Impact Factor-2019: 9.3
Publication date: 2021
Journal article

Wireless Interface agent for SDN mmWave multi-hop networks: design and experimental evaluation
2nd ACM Workshop on Millimeter Wave Networks and Sensing Systems
Presentation date: 10/2018
Presentation of work at congresses

Deploying a containerized ns-3/LENA-based LTE mobile Network Service through the 5G-TRANSFORMER platform
2018 IEEE Conference on Network Function Virtualization and Software Defined Networks
Presentation date: 11/2018
Presentation of work at congresses

5G-TRANSFORMER service orchestrator: design implementation and evaluation
2019 European Conference on Networks and Communications
Presentation date: 06/2019
Presentation of work at congresses

Demo: composing services in 5G-TRANSFORMER
Twentieth ACM International Symposium on Mobile Ad Hoc Networking and Computing
Presentation date: 07/2019
Presentation of work at congresses

Automated deployment and scaling of automotive safety services in 5G-Transformer
2019 IEEE Conference on Network Function Virtualization and Software Defined Networks
Presentation date: 11/2019
Presentation of work at congresses

A mobile transport platform interconnecting VNFs over a multi-domain optical/wireless network: design and implementation
24th International Conference on Optical Network Design and Modeling
Presentation date: 05/2020
Presentation of work at congresses

5G-TRANSFORMER meets Network Service Federation: design, implementation and evaluation
2020 6th IEEE Conference on Network Softwarization (Netsoft)
Presentation date: 06/2020
Presentation of work at congresses

Arbitrating Network Services in 5G Networks for Automotive Vertical Industry
IEEE International Conference on Computer Communications
Presentation date: 07/2020
Presentation of work at congresses

NFV Service Federation: enabling Multi-Provider eHealth Emergency Services
IEEE International Conference on Computer Communications
Presentation date: 07/2020
Presentation of work at congresses

Scaling composite NFV-network services
ACM International Symposium on Mobile Ad Hoc Networking and Computing
Presentation date: 10/2020
Presentation of work at congresses

On the Integration of AI/ML-based scaling operations in the 5Growth platform
IEEE Conference on Network Function Virtualization and Software Defined Networks
Presentation date: 11/11/2020
Presentation of work at congresses

Demo: AIML-as-a-Service for SLA management of a Digital Twin Virtual Network Service
Annual IEEE Conference on Computer Communications 2021
Presentation date: 05/2021
Presentation of work at congresses

Scaling Federated Network Services: Managing SLAs in Multi-Provider Industry 4.0 Scenarios
Annual IEEE Conference on Computer Communications 2021
Presentation date: 05/2021
Presentation of work at congresses

Experimental Validation of Compute and Network Resource Abstraction and Allocation Mechanisms within an NFV Infrastructure
IFIP/IEEE International Symposium on Integrated Network Management
Presentation date: 05/2021
Presentation of work at congresses

AUTHOR:BECERRA SÁNCHEZ, ENRIQUETA PATRICIA
Title:Development of cognitive workload models to detect driving impairment
Reading date:20/09/2021
Director:REYES MUÑOZ, MARIA ANGELICA
Mention:No mention
RELATED PUBLICATIONS
Wearable sensors for evaluating driver drowsiness and high stress
Becerra, E.; Reyes, M.; Guerrero , J.
IEEE Latin America transactions, ISSN: 1548-0992 (JCR Impact Factor-2019: 0.782; Quartil: Q4)
Publication date: 2019
Journal article

Feature selection model based on EEG signals for assessing the cognitive workload in drivers
Becerra, E.; Reyes, M.; Guerrero, J.
Sensors (Switzerland), ISSN: 1424-8220 (JCR Impact Factor-2020: 3.576; Quartil: Q1)
Publication date: 17/10/2020
Journal article

AUTHOR:PAILLISSÉ VILANOVA, JORDI
Title:Next generation overlay networks: security, trust, and deployment challenges
Reading date:23/07/2021
Director:CABELLOS APARICIO, ALBERTO
Co-director:MAINO, FABIO
Mention:International Mention
RELATED PUBLICATIONS
Programmable overlays via OpenOverlayRouter
Rodriguez, A.; Paillisse, J.; Coras, F.; Lopez, A.; Jakab, L.; Marc Portoles-Comeras; Natarajan , P.; Meyer, D.; Farinacci, D.; Maino, F.; Albert Cabellos-Aparicio; Ermagan, V.
IEEE communications magazine, ISSN: 0163-6804 (JCR Impact Factor-2017: 9.27; Quartil: Q1)
Publication date: 01/06/2017
Journal article

Decentralized trust in the inter-domain routing infrastructure
Paillisse, J.; Manrique, J.; Bonet, G.; Rodríguez, A.; Maino, F.; Albert Cabellos-Aparicio
IEEE access, ISSN: 2169-3536 (JCR Impact Factor-2019: 3.745; Quartil: Q1)
Publication date: 01/01/2019
Journal article

ALLIANCE Project: Architecting a Knowledge-Defined 5G-Enabled Network Infrastructure
20th International Conference on Transparent Optical Networks
Presentation date: 04/07/2018
Presentation of work at congresses

IPchain: securing IP prefix allocation and delegation with blockchain
14th IEEE International Conference on Green Computing and Communications
Presentation date: 08/2018
Presentation of work at congresses

Distributed access control with blockchain
2019 IEEE International Conference on Communications
Presentation date: 21/05/2019
Presentation of work at congresses

SD-access: practical experiences in designing and deploying software defined enterprise networks
16th International Conference on Emerging Networking Experiments and Technologies
Presentation date: 12/2020
Presentation of work at congresses

A control plane for WireGuard
30th International Conference on Computer Communications and Networks
Presentation date: 07/2021
Presentation of work at congresses

AUTHOR:BOSCH PONS, JAUME
Title:Breaking host-centric management of Task-Based Parallel Programming Models
Reading date:21/07/2021
Director:ALVAREZ MARTINEZ, CARLOS
Co-director:JIMENEZ GONZALEZ, DANIEL
Mention:No mention
RELATED PUBLICATIONS
A hardware runtime for task-based programming models
Tan, X.; Bosch, Jaume; Alvarez, C.; Jimenez, D.; Ayguade, E.; Valero, M.
IEEE transactions on parallel and distributed systems, ISSN: 1045-9219 (JCR Impact Factor-2019: 2.6; Quartil: Q2)
Publication date: 01/09/2019
Journal article

Asynchronous runtime with distributed manager for task-based programming models
Bosch, Jaume; Alvarez, C.; Jimenez, D.; Martorell, X.; Ayguade, E.
Parallel computing, ISSN: 0167-8191 (JCR Impact Factor-2020: 0.986; Quartil: Q3)
Publication date: 09/2020
Journal article

OmpSs@FPGA framework for high performance FPGA computing
De Haro, J.; Bosch, Jaume; Filgueras, A.; Vidal, Miquel; Jimenez, D.; Alvarez, C.; Martorell, X.; Ayguade, E.; Labarta, J.
IEEE transactions on computers, ISSN: 0018-9340 (JCR Impact Factor-2019: 2.711; Quartil: Q2)
Publication date: 01/12/2021
Journal article

TaskGenX: A hardware-software proposal for accelerating task parallelism
International Conference on High Performance Computing 2018
Presentation date: 06/2018
Presentation of work at congresses

Asynchronous task creation for task-based parallel programming
2018 OpenMP Developers Conference
Presentation date: 09/2018
Presentation of work at congresses

Supporting task creation inside FPGA devices
6th BSC Severo Ochoa Doctoral Symposium
Presentation date: 07/05/2019
Presentation of work at congresses

Application Acceleration on FPGAs with OmpSs@FPGA
2018 International Conference on Field-Programmable Technology
Presentation date: 10/12/2018
Presentation of work at congresses

Adding tightly-integrated task scheduling acceleration to a RISC-V multi-core processor
52th Annual IEEE/ACM International Symposium on Microarchitecture
Presentation date: 10/2019
Presentation of work at congresses

Breaking master-slave model between host and FPGAs
25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Presentation date: 19/02/2020
Presentation of work at congresses

Design and implementation of an architecture-aware hardware runtime for heterogeneous systems
7th BSC Severo Ochoa Doctoral Symposium 2020
Presentation date: 05/2020
Presentation of work at congresses

Task-based programming models for heterogeneous recurrent workloads
17th International Symposium on Applied Reconfigurable Computing
Presentation date: 30/06/2021
Presentation of work at congresses

AUTHOR:TAGHVAEE, HAMIDREZA
Title:On scalable, reconfigurable, and intelligent metasurfaces
Reading date:21/07/2021
Director:CABELLOS APARICIO, ALBERTO
Co-director:ABADAL CAVALLÉ, SERGI
Mention:International Mention
RELATED PUBLICATIONS
The scaling laws of HyperSurfaces
Taghvaee, H.; S. Abadal; Alarcon, E.; Albert Cabellos-Aparicio; Saeed, T.; Pitsillides, A.; Tsilipakos, O.; Liaskos, C.; Tasolamprou, A.; Kafesaki, M.; Pitilakis, A.; Kantartzis, N.; Soteriou, V.; Lestas, M.
CRC Press
Publication date: 2020
Book chapter

Exploration of intercell wireless millimeter-wave communication in the landscape of intelligent metasurfaces
Tasolamprou, A.; Pitilakis, A.; S. Abadal; Tsilipakos, O.; Timoneda, X.; Taghvaee, H.; Mirmoosa, M.; Liu, F.; Liaskos, C.; Tsioliaridou, A.; Ioannidis, S.; Kantartzis, N.; Manessis, D.; Albert Cabellos-Aparicio; Alarcon, E.
IEEE access, ISSN: 2169-3536 (JCR Impact Factor-2019: 3.745; Quartil: Q1)
Publication date: 01/01/2019
Journal article

Scalability analysis of programmable metasurfaces for beam steering
Taghvaee, H.; S. Abadal; Pitilakis, A.; Tsilipakos, O.; Tasolamprou, A.; Liaskos, C.; Kafesaki, M.; Kantartzis, N.; Albert Cabellos-Aparicio; Alarcon, E.
IEEE access, ISSN: 2169-3536 (JCR Impact Factor-2020: 3.367; Quartil: Q2)
Publication date: 01/01/2020
Journal article

Toward intelligent metasurfaces: the progress from globally tunable metasurfaces to software-defined metasurfaces with an embedded network of controllers
Tsilipakos, O.; Tasolamprou, A.; Pitilakis, A.; Liu, F.; Wang, X.; Mirmoosa, M.; Tzarouchis, D.; S. Abadal; Taghvaee, H.; Liaskos, C.; Tsioliaridou, A.; Georgiou, J.; Albert Cabellos-Aparicio; Alarcon, E.; Ioannidis, S.; Pitsillides, A.; Akyildiz, I.; Kantartzis, N.; Economou, E.; Soukoulis, C.; Kafesaki, M.; Tretyakov, S.
Advanced optical materials, ISSN: 2195-1071 (JCR Impact Factor-2020: 9.926; Quartil: Q1)
Publication date: 01/01/2020
Journal article

Error analysis of programmable metasurfaces for beam steering
Taghvaee, H.; Albert Cabellos-Aparicio; Georgiou, J.; S. Abadal
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, ISSN: 2156-3357 (JCR Impact Factor-2020: 3.916; Quartil: Q1)
Publication date: 01/03/2020
Journal article

Radiation pattern prediction for metasurfaces: A neural network-based approach
Taghvaee, H.; Jain, A.; Timoneda i, X.; Liaskos, C.; S. Abadal; Alarcon, E.; Albert Cabellos-Aparicio
Sensors (Switzerland), ISSN: 1424-8220 (JCR Impact Factor-2019: 5.0
Publication date: 14/04/2021
Journal article

Workload characterization and traffic analysis for reconfigurable intelligent surfaces within 6G wireless systems
Saeed, T.; S. Abadal; Liaskos, C.; Pitsillides, A.; Taghvaee, H.; Albert Cabellos-Aparicio; Soteriou, V.; Alarcon, E.; Akyildiz, I.; Lestas, M.
IEEE transactions on mobile computing, ISSN: 1536-1233 (JCR Impact Factor-2020: 5.538; Quartil: Q1)
Publication date: 13/11/2021
Journal article

Subwavelength focusing by engineered power-flow conformal metamirrors
Taghvaee, H.; Liu, F.; Tretyakov, S.; Díaz, A.
Physical review B, ISSN: 2469-9969 (JCR Impact Factor-2020: 6.5
Publication date: 15/12/2021
Journal article

Multiwideband Terahertz Communications Via Tunable Graphene-Based Metasurfaces in 6G Networks: Graphene Enables Ultimate Multiwideband THz Wavefront Control
Taghvaee, H.; Pitilakis, A.; Tsilipakos, O.; Tasolamprou, A.; Kantartzis, N.; Kafesaki, M.; Albert Cabellos-Aparicio; Alarcon, E.; S. Abadal
IEEE Vehicular Technology Magazine, ISSN: 1556-6080 (JCR Impact Factor-2020: 10.384; Quartil: Q1)
Publication date: 01/01/2022
Journal article

On the use of genetic algorithm to design and optimize graphene-based absorbers
Nanophotonics and Micro/Nano Optics International Conference 2018
Presentation date: 01/10/2018
Presentation of work at congresses

Opportunistic beamforming in wireless network-on-chip
2019 IEEE International Symposium on Circuits and Systems
Presentation date: 05/2019
Presentation of work at congresses

Fault tolerance in programmable metasurfaces: the beam steering case
2019 IEEE International Symposium on Circuits and Systems
Presentation date: 2019
Presentation of work at congresses

Workload characterization of programmable metasurfaces
6th ACM International Conference on Nanoscale Computing and Communication
Presentation date: 09/2019
Presentation of work at congresses

Extremum seeking control for beam steering using hypersurfaces
IEEE International Conference on Communications 2020
Presentation date: 06/2020
Presentation of work at congresses

On the use of programmable metasurfaces in vehicular networks
22nd IEEE International Workshop on Signal Processing Advances in Wireless Communications
Presentation date: 09/2021
Presentation of work at congresses

Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH)
18th ACM International Conference on Computing Frontiers
Presentation date: 13/05/2021
Presentation of work at congresses

AUTHOR:BARREDO FERREIRA, ADRIÁN
Title:Novel techniques to improve the performance and the energy of vector architectures
Reading date:19/07/2021
Director:MORETÓ PLANAS, MIQUEL
Co-director:ARMEJACH SANOSA, ADRIÀ
Mention:International Mention
RELATED PUBLICATIONS
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies
Barredo, A.; Cebrián González, Juan Manuel; Valero, M.; Casas, M.; Moreto, M.
Journal of supercomputing, ISSN: 0920-8542 (JCR Impact Factor-2020: 2.474; Quartil: Q2)
Publication date: 03/2020
Journal article

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86
Cebrián González, Juan Manuel; Barredo, A.; Caminal, H.; Moreto, M.; Casas, M.; Valero, M.
Future generation computer systems, ISSN: 0167-739X (JCR Impact Factor-2020: 7.187; Quartil: Q1)
Publication date: 11/2020
Journal article

Compiler-assisted compaction/restoration of SIMD instructions
Cebrián, J.; Balem, T.; Barredo, A.; Casas, M.; Moreto, M.; Ros Bardisa, Alberto; Jimborean, A.
IEEE transactions on parallel and distributed systems, ISSN: 1045-9219 (JCR Impact Factor-2019: 9.2
Publication date: 01/04/2022
Journal article

POSTER: SPiDRE: accelerating sparse memory access patterns
28th International Conference on Parallel Architectures and Compilation Techniques
Presentation date: 09/2019
Presentation of work at congresses

An optimized predication execution for SIMD extensions
28th International Conference on Parallel Architectures and Compilation Techniques
Presentation date: 09/2019
Presentation of work at congresses

Improving predication efficiency through compaction/restoration of SIMD instructions
HPCA 2020 - 27th International Symposium on High-Performance Computer Architecture
Presentation date: 2020
Presentation of work at congresses

PLANAR: a programmable accelerator for near-memory data rearrangement
35th International Conference on Supercomputing
Presentation date: 06/2021
Presentation of work at congresses

VIA: A smart scratchpad for vector units with application to sparse matrix computations
27th International Symposium on High Performance Computer Architecture
Presentation date: 2021
Presentation of work at congresses

AUTHOR:D'AMICO, MARCO
Title:Scheduling and resource management solutions for the scalable and efficient design of today's and tomorrow's HPC machines
Reading date:10/06/2021
Director:CORBALAN GONZALEZ, JULITA
Co-director:JOKANOVIC, ANA
Mention:International Mention
RELATED PUBLICATIONS
Evaluating SLURM simulator with real-machine SLURM and vice versa
2018 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems
Presentation date: 2018
Presentation of work at congresses

DJSB: Dynamic Job Scheduling Benchmark
21st Workshop on Job Scheduling Strategies for Parallel Processing
Presentation date: 06/2017
Presentation of work at congresses

DROM: Enabling efficient and effortless malleability for resource managers
47th International Conference on Parallel Processing
Presentation date: 13/08/2018
Presentation of work at congresses

Holistic slowdown driven scheduling and resource management for malleable jobs
48th International Conference on Parallel Processing
Presentation date: 06/08/2019
Presentation of work at congresses

AUTHOR:BELLVER BUENO, MÍRIAM
Title:Image and video object segmentation in low supervision scenarios
Reading date:26/03/2021
Director:TORRES VIÑALS, JORDI
Co-director:GIRÓ NIETO, XAVIER
Mention:No mention
RELATED PUBLICATIONS
Mask-guided sample selection for semi-supervised instance segmentation
Bellver, M.; Salvador, A.; Torres, J.; Giro, X.
Multimedia tools and applications, ISSN: 1380-7501 (JCR Impact Factor-2020: 2.757; Quartil: Q2)
Publication date: 05/07/2020
Journal article

Hierarchical object detection with deep reinforcement learning
Third Deep Reinforcement Learning Workshop
Presentation date: 16/12/2016
Presentation of work at congresses

Distributed training strategies for a computer vision deep learning algorithm on a distributed GPU cluster
International Conference on Computational Science 2017
Presentation date: 14/06/2017
Presentation of work at congresses

Detection-aided liver lesion segmentation using deep learning
Machine Learning for Health Workshop at NIPS 2017
Presentation date: 08/12/2017
Presentation of work at congresses

RVOS: end-to-end recurrent network for video object segmentation
2019 IEEE Conference on Computer Vision and Pattern Recognition
Presentation date: 19/06/2019
Presentation of work at congresses

Budget-aware semi-supervised semantic and instance segmentation
2019 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops
Presentation date: 16/06/2019
Presentation of work at congresses

AUTHOR:SEGURA SALVADOR, ALBERT
Title:High-performance and energy-efficient irregular graph processing on GPU architectures
Reading date:18/02/2021
Director:ARNAU MONTAÑES, JOSÉ MARÍA
Co-director:GONZÁLEZ COLÁS, ANTONIO MARIA
Mention:No mention
RELATED PUBLICATIONS
Low-power automatic speech recognition through a mobile GPU and a Viterbi accelerator
Yazdani, R.; Segura, A.; Arnau, J.; Gonzalez, A.
IEEE micro, ISSN: 0272-1732 (JCR Impact Factor-2017: 1.913; Quartil: Q2)
Publication date: 12/04/2017
Journal article

An ultra low-power hardware accelerator for automatic speech recognition
49th Annual IEEE/ACM Symposium on Microarchitecture
Presentation date: 17/10/2016
Presentation of work at congresses

SCU: a GPU stream compaction unit for graph processing
46th International Symposium on Computer Architecture
Presentation date: 24/06/2019
Presentation of work at congresses

AUTHOR:MAROÑAS BRAVO, MARCOS
Title:On the design and development of programming models for exascale systems
Reading date:17/02/2021
Director:BELTRAN QUEROL, VICENÇ
Co-director:AYGUADÉ PARRA, EDUARD
Mention:International Mention
RELATED PUBLICATIONS
Extending the OpenCHK Model with advanced checkpoint features
Maroñas, M.; Mateo, S.; Keller, K.; Bautista Gomez, Leonardo Arturo; Ayguade, E.; Beltran, V.
Future generation computer systems, ISSN: 0167-739X (JCR Impact Factor-2020: 7.187; Quartil: Q1)
Publication date: 11/2020
Journal article

Worksharing tasks: An efficient way to exploit irregular and fine-grained loop parallelism
IEEE 26th International Conference on High Performance Computing, Data, and Analytics
Presentation date: 12/2019
Presentation of work at congresses

Evaluating worksharing tasks on distributed environments
22nd IEEE International Conference on Cluster Computing
Presentation date: 09/2020
Presentation of work at congresses

AUTHOR:SILFA FELIZ, FRANYELL ANTONIO
Title:Energy-efficient architectures for recurrent neural networks
Reading date:25/01/2021
Director:ARNAU MONTAÑES, JOSÉ MARÍA
Co-director:GONZÁLEZ COLÁS, ANTONIO MARIA
Mention:No mention
RELATED PUBLICATIONS
Neuron-level fuzzy memoization in RNNs
52th Annual IEEE/ACM International Symposium on Microarchitecture
Presentation date: 14/10/2019
Presentation of work at congresses

Boosting LSTM performance through dynamic precision selection
27th International Conference on High Performance Computing, Data, and Analytics
Presentation date: 16/12/2020
Presentation of work at congresses

AUTHOR:BUCHACA PRATS, DAVID
Title:Learning workload behaviour models from monitored time-series for resource estimation towards data center optimization
Reading date:14/01/2021
Tutor/a:BECERRA FONTAL, YOLANDA
Director:CARRERA PÉREZ, DAVID
Co-director:BERRAL GARCÍA, JOSEP LLUÍS
Mention:International Mention
RELATED PUBLICATIONS
A highly parameterizable framework for Conditional Restricted Boltzmann Machine based workloads accelerated with FPGAs and OpenCL
Jaksic, Z.; Cadenelli, N.; Buchaca, D.; Polo, J.; Berral, J.; Carrera, D.
Future generation computer systems, ISSN: 0167-739X (JCR Impact Factor-2020: 7.187; Quartil: Q1)
Publication date: 01/03/2020
Journal article

Improving maritime traffic emission estimations on missing data with CRBMs
Gutierrez-Torre, A.; Berral, J.; Buchaca, D.; Guevara, M.; Soret, A.; Carrera, D.
Engineering applications of artificial intelligence, ISSN: 0952-1976 (JCR Impact Factor-2020: 6.212; Quartil: Q1)
Publication date: 07/07/2020
Journal article

Sequence-to-sequence models for workload interference prediction on batch processing datacenters
Buchaca, D.; Marcual, J.; Berral, J.; Carrera, D.
Future generation computer systems, ISSN: 0167-739X (JCR Impact Factor-2020: 7.187; Quartil: Q1)
Publication date: 09/2020
Journal article

You only run once: Spark auto-tuning from a single run
Buchaca, D.; Albuquerque, F.; Costa, C.; Berral, J.
IEEE transactions on network and service management, ISSN: 1932-4537 (JCR Impact Factor-2020: 4.195; Quartil: Q2)
Publication date: 12/2020
Journal article

Proactive container auto-scaling for cloud native machine learning services
13th IEEE International Conference on Cloud Computing
Presentation date: 10/2020
Presentation of work at congresses

Theta-Scan: Leveraging behavior-driven forecasting for vertical auto-scaling in container cloud
14th IEEE International Conference on Cloud Computing
Presentation date: 2021
Presentation of work at congresses

AUTHOR:CAMPOS CAMÚÑEZ, VÍCTOR
Title:Deep learning that scales: Leveraging compute and data
Reading date:22/12/2020
Director:TORRES VIÑALS, JORDI
Co-director:GIRÓ NIETO, XAVIER
Mention:No mention
RELATED PUBLICATIONS
Is a “happy dog” more “happy” than “dog”? - Adjective and Noun Contributions for Adjective-Noun Pair prediction
11th Women in Machine Learning Workshop
Presentation date: 05/12/2016
Presentation of work at congresses

Scaling a convolutional neural network for classification of adjective noun pairs with TensorFlow on GPU clusters
17th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing
Presentation date: 14/05/2017
Presentation of work at congresses

Importance weighted evolution strategies
Deep Reinforcement Learning Workshop 2018
Presentation date: 07/12/2018
Presentation of work at congresses

Skip RNN: learning to skip state updates in recurrent neural networks
6th International Conference on Learning Representations
Presentation date: 03/05/2018
Presentation of work at congresses

Comparing fixed and adaptive computation time for recurrent neural networks
6th International Conference on Learning Representations
Presentation date: 01/05/2018
Presentation of work at congresses

How to initialize your network? Robust initialization for WeightNorm & ResNets
33rd Annual Conference on Neural Information Processing Systems
Presentation date: 05/12/2019
Presentation of work at congresses

Explore, discover and learn: unsupervised discovery of state-covering skills
37th International Conference on Machine Learning
Presentation date: 14/07/2020
Presentation of work at congresses

AUTHOR:CIACCIA, FRANCESCO
Title:Definition of new WAN paradigms enabled by smart measurements
Reading date:04/12/2020
Director:SERRAL GRACIÀ, RENÉ
Co-director:NEMIROVSKY, MARIO DANIEL
Mention:Industrial Doctorate Mention
RELATED PUBLICATIONS
Intelligent adaptive transport layer to enhance performance using multiple channels
Registration date: 18/06/2017
Patent

Improving TCP performance and reducing self-induced congestion with receive window modulation
28th International Conference on Computer Communications and Networks
Presentation date: 01/08/2019
Presentation of work at congresses

SABES: Statistical Available Bandwidth EStimation from passive TCP measurements
19th IFIP Networking Conference
Presentation date: 22/06/2020
Presentation of work at congresses

HIRE: Hidden Inter-packet Red-shift Effect
2020 IEEE Global Communications Conference
Presentation date: 11/12/2020
Presentation of work at congresses

AUTHOR:TRILLA RODRÍGUEZ, DAVID
Title:Non-functional considerations of time-randomized processor architectures
Reading date:04/12/2020
Tutor/a:CAZORLA ALMEIDA, FRANCISCO JAVIER
Director:ABELLA FERRER, JAIME
Co-director:HERNANDEZ LUZ, CARLES
Mention:International Mention
RELATED PUBLICATIONS
Worst-case energy consumption: A new challenge for battery-powered critical devices
Trilla, D.; Hernández, C.; Abella, J.; Cazorla, F. J.
IEEE transactions on sustainable computing, ISSN: 2377-3782
Publication date: 01/07/2021
Journal article

Modeling the impact of process variations in worst-case energy consumption estimation
22nd Euromicro Conference on Digital System Design
Presentation date: 08/2019
Presentation of work at congresses

An approach for detecting power peaks during testing and breaking systematic pathological behavior
22nd Euromicro Conference on Digital System Design
Presentation date: 08/2019
Presentation of work at congresses

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping
27th IEEE International Symposium on On-Line Testing and Robust System Design
Presentation date: 06/2021
Presentation of work at congresses

SafeSU: an extended statistics unit for multicore timing interference
26th IEEE European Test Symposium
Presentation date: 05/2021
Presentation of work at congresses

AUTHOR:DIMIC, VLADIMIR
Title:Runtime-assisted optimizations in the on-chip memory hierarchy
Reading date:27/11/2020
Director:MORETÓ PLANAS, MIQUEL
Co-director:CASAS GUIX, MARC
Mention:No mention
RELATED PUBLICATIONS
Runtime-assisted shared cache insertion policies based on re-reference intervals
23rd International European Conference on Parallel and Distributed Computing
Presentation date: 30/08/2017
Presentation of work at congresses

RICH: implementing reductions in the cache hierarchy
34th International Conference on Supercomputing
Presentation date: 06/2020
Presentation of work at congresses

PrioRAT: criticality-driven prioritization inside the on-chip memory hierarchy
27th International European Conference on Parallel and Distributed Computing
Presentation date: 09/2021
Presentation of work at congresses

AUTHOR:SENGUPTA, SOUVIK
Title:Adaptive learning-based resource management strategy in fog-to-cloud
Reading date:20/10/2020
Director:GARCÍA ALMIÑANA, JORDI
Co-director:MASIP BRUIN, JAVIER
Mention:No mention
RELATED PUBLICATIONS
Essentiality of managing the resource information in the coordinated fog-to-cloud paradigm
Sengupta, S.; Garcia, J.; Masip, X.
International journal of communication systems, ISSN: 1074-5351 (JCR Impact Factor-2019: 1.319; Quartil: Q3)
Publication date: 26/12/2019
Journal article

An architectural schema for performance prediction using machine learning in the fog-to-cloud paradigm
2019 IEEE 10th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference
Presentation date: 10/2019
Presentation of work at congresses

SFDDM: a secure distributed database management in combined fog-to-cloud systems
2019 IEEE 24th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks
Presentation date: 09/2019
Presentation of work at congresses

Collaborative learning-based schema for predicting resource usage and performance in F2C paradigm
14th IEEE International Conference on Advanced Networks and Telecommunications Systems
Presentation of work at congresses

AUTHOR:RIERA VILLANUEVA, MARC
Title:Low-power accelerators for cognitive computing
Reading date:09/10/2020
Director:ARNAU MONTAÑES, JOSÉ MARÍA
Co-director:GONZÁLEZ COLÁS, ANTONIO MARIA
Mention:No mention
RELATED PUBLICATIONS
CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference
Riera, M.; Arnau, J.; Gonzalez, A.
IEEE micro, ISSN: 0272-1732 (JCR Impact Factor-2019: 3.172; Quartil: Q1)
Publication date: 01/09/2019
Journal article

Computation reuse in DNNs by exploiting input similarity
The 45th International Symposium on Computer Architecture
Presentation date: 19/07/2018
Presentation of work at congresses

The dark side of DNN pruning
The 45th International Symposium on Computer Architecture
Presentation date: 02/06/2018
Presentation of work at congresses

AUTHOR:RAMÓN-CORTÉS VILARRODONA, CRISTIÁN
Title:Programming models to support data science workflows
Reading date:28/09/2020
Director:BADIA SALA, ROSA MARIA
Co-director:EJARQUE ARTIGAS, JORGE
Mention:International Mention
RELATED PUBLICATIONS
Executing linear algebra kernels in heterogeneous distributed infrastructures with PyCOMPSs
Amela, R.; Cristián Ramón-Cortés Vilarrodona; Ejarque, J.; Conejero, J.; Badia, R.M.
Oil and gas science and technology. Revue de l'Institut Français du Pétrole, ISSN: 1294-4475 (JCR Impact Factor-2018: 1.867; Quartil: Q1)
Publication date: 2018
Journal article

Transparent orchestration of task-based parallel applications in containers platforms
Cristián Ramón-Cortés Vilarrodona; Serven, A.; Ejarque, J.; Lezzi, D.; Badia, R.M.
Journal of grid computing, ISSN: 1570-7873 (JCR Impact Factor-2018: 3.288; Quartil: Q1)
Publication date: 01/02/2018
Journal article

AutoParallel: Automatic parallelisation and distributed execution of affine loop nests in Python
Cristián Ramón-Cortés Vilarrodona; Amela, R.; Ejarque, J.; Clauss, P.; Badia, R.M.
The international journal of high performance computing applications (IJHPCA), ISSN: 1741-2846 (JCR Impact Factor-2020: 1.942; Quartil: Q2)
Publication date: 2020
Journal article

A programming model for hybrid workflows: combining task-based workflows and dataflows all-in-one
Cristián Ramón-Cortés Vilarrodona; Lordan, F.; Ejarque, J.; Badia, R.M.
Future generation computer systems, ISSN: 0167-739X (JCR Impact Factor-2020: 7.187; Quartil: Q1)
Publication date: 12/2020
Journal article

The impact of non-additive genetic associations on age-related complex diseases
Guindo, M.; Amela, R.; Bonàs-Guarch, S.; Puiggros, M.; Salvoro, C.; Miguel-Escalada, I.; Sánchez, F.; Cristián Ramón-Cortés Vilarrodona; Badia, R.M.; Ejarque, J.; Mercader, J.; Torrents , D.
Nature communications, ISSN: 2041-1723 (JCR Impact Factor-2019: 18.1
Publication date: 23/04/2021
Journal article

Enabling Python to execute efficiently in heterogeneous distributed infrastructures with PyCOMPSs
7th Workshop on Python for High-Performance and Scientific Computing
Presentation date: 11/11/2017
Presentation of work at congresses

Boosting atmospheric dust forecast with PyCOMPSs
14th IEEE International Conference on e-Science
Presentation date: 11/2018
Presentation of work at congresses

AUTHOR:REJIBA, ZEINEB
Title:Mobility-aware mechanisms for fog node discovery and selection
Reading date:10/09/2020
Director:MASIP BRUIN, JAVIER
Co-director:MARIN TORDERA, EVA
Mention:No mention
RELATED PUBLICATIONS
A user-centric mobility management scheme for high-density fog computing deployments
28th International Conference on Computer Communications and Networks
Presentation date: 30/07/2019
Presentation of work at congresses

Computation task assignment in vehicular fog computing: a learning approach via neighbor advice
18th IEEE International Symposium on Network Computing and Applications
Presentation date: 26/09/2019
Presentation of work at congresses

AUTHOR:SUÁREZ-VARELA MACIÁ, JOSÉ RAFAEL
Title:Enabling knowledge-defined networks: Deep reinforcement learning, graph neural networks and network analytics
Reading date:26/06/2020
Director:BARLET ROS, PERE
Co-director:CABELLOS APARICIO, ALBERTO
Mention:International Mention
RELATED PUBLICATIONS
Flow monitoring in software-defined networks: finding the accuracy/performance tradeoffs
Suarez-varela, J.; Barlet, P.
Computer networks, ISSN: 1389-1286 (JCR Impact Factor-2018: 3.03; Quartil: Q1)
Publication date: 22/04/2018
Journal article

Routing in optical transport networks with deep reinforcement learning
Suarez-varela, J.; Mestres, A.; Yu, J.; Kuang, L.; Feng, H.; Albert Cabellos-Aparicio; Barlet, P.
Journal of optical communications and networking, ISSN: 1943-0620 (JCR Impact Factor-2019: 3.425; Quartil: Q1)
Publication date: 2019
Journal article

RouteNet: leveraging graph neural networks for network modeling and optimization in SDN
Rusek, K.; Suarez-varela, J.; Almasan, P.; Barlet, P.; Albert Cabellos-Aparicio
IEEE journal on selected areas in communications, ISSN: 0733-8716 (JCR Impact Factor-2020: 9.144; Quartil: Q1)
Publication date: 05/06/2020
Journal article

Unveiling the potential of Graph Neural Networks for network modeling and optimization in SDN
5th Symposium on SDN Research
Presentation date: 04/04/2019
Presentation of work at congresses

Feature engineering for deep reinforcement learning based routing
2019 IEEE International Conference on Communications
Presentation date: 21/05/2019
Presentation of work at congresses

Detecting cryptocurrency miners with NetFlow/IPFIX network measurements
5th IEEE International Workshop on Measurements and Networking
Presentation date: 08/07/2019
Presentation of work at congresses

Challenging the generalization capabilities of Graph Neural Networks for network modeling
ACM Conference on Special Interest Group on Data Communication 2019
Presentation date: 21/08/2019
Presentation of work at congresses

Towards more realistic network models based on Graph Neural Networks
15th International Conference on Emerging Networking Experiments and Technologies
Presentation date: 09/12/2019
Presentation of work at congresses

Is machine learning ready for traffic engineering optimization?
29th IEEE International Conference on Network Protocols
Presentation date: 02/11/2021
Presentation of work at congresses

AUTHOR:ANGLADA SÁNCHEZ, MARTÍ
Title:Exploiting frame coherence in real-time rendering for energy-efficient GPUs.
Reading date:09/06/2020
Director:GONZÁLEZ COLÁS, ANTONIO MARIA
Co-director:PARCERISA BUNDO, JOAN MANUEL
Mention:No mention
RELATED PUBLICATIONS
SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems
Vallero, A.; Savino, A.; Chatzidimitriou, A.; Kaliorakis, M.; Kooli, M.; Riera, M.; Anglada, M.; Di Natale, G.; Bosio, A.; Canal, R.; Gonzalez, A.; Gizopoulos, D.; Mariani, R.; Stefano Di Carlo
IEEE transactions on computers, ISSN: 0018-9340 (JCR Impact Factor-2018: 3.131; Quartil: Q1)
Publication date: 18/12/2018
Journal article

AUTHOR:NARO, DANIEL
Title:Security strategies in genomic files
Reading date:15/05/2020
Director:DELGADO MERCE, JAIME M.
Co-director:LLORENTE VIEJO, SILVIA
Mention:No mention
RELATED PUBLICATIONS
Reversible fingerprinting for genomic information
Naro, D.; Delgado, J.; Llorente, S.
Multimedia tools and applications, ISSN: 1380-7501 (JCR Impact Factor-2020: 2.757; Quartil: Q2)
Publication date: 03/01/2020
Journal article

Side channel attack on a partially encrypted MPEG-G file
Naro, D.; Delgado, J.; Llorente, S.
Multimedia tools and applications, ISSN: 1380-7501 (JCR Impact Factor-2019: 2.313; Quartil: Q2)
Publication date: 05/2021
Journal article

AUTHOR:SEMBROIZ AUSEJO, DAVID
Title:Ambient intelligence in buildings. Design and development of an interoperable Internet of Things platform
Reading date:06/03/2020
Director:CAREGLIO, DAVIDE
Co-director:RICCIARDI, SERGIO
Mention:No mention
RELATED PUBLICATIONS
Chapter 10- A novel cloud-based IoT architecture for smart building automation
Sembroiz, D.; Ricciardi, S.; Careglio, D.
Elsevier
Publication date: 2018
Book chapter

A GRASP meta-heuristic for evaluating the latency and lifetime impact of critical nodes in large wireless sensor networks
Sembroiz, D.; Ojaghi Kahjogh, B.; Careglio, D.; Ricciardi, S.
Applied sciences (Basel), ISSN: 2076-3417 (JCR Impact Factor-2019: 2.474; Quartil: Q2)
Publication date: 01/11/2019
Journal article

AUTHOR:CADENELLI, NICOLA
Title:Hardware/software co-design for data-intensive genomics workloads
Reading date:19/12/2019
Tutor/a:BECERRA FONTAL, YOLANDA
Director:CARRERA PÉREZ, DAVID
Co-director:POLO BARDÉS, JORDÀ
Mention:No mention
RELATED PUBLICATIONS
Enabling genomics pipelines in commodity personal computers with flash storage
Cadenelli, N.; Jun, S.; Polo, J.; Wright, A.; Carrera, D.; Mithal, A.
Frontiers in genetics, ISSN: 1664-8021 (JCR Impact Factor-2019: 3.258; Quartil: Q2)
Publication date: 04/2021
Journal article

AUTHOR:MILUTINOVIC, SUZANA
Title:On the limits of probabilistic timing analysis
Reading date:18/12/2019
Director:CAZORLA ALMEIDA, FRANCISCO JAVIER
Co-director:ABELLA FERRER, JAIME
Mention:International Mention
RELATED PUBLICATIONS
Increasing the reliability of software timing analysis for cache-based processors
Milutinovic, S.; Mezzetti, Enrico; Abella, J.; Cazorla, F. J.
IEEE transactions on computers, ISSN: 0018-9340 (JCR Impact Factor-2019: 2.711; Quartil: Q2)
Publication date: 01/06/2019
Journal article

Measurement-based cache representativeness on multipath programs
55rd Design Automation Conference
Presentation date: 06/2018
Presentation of work at congresses

AUTHOR:BAIG, SHUJA-UR-REHMAN
Title:Data center's telemetry reduction and prediction through modeling techniques
Reading date:17/12/2019
Tutor/a:BECERRA FONTAL, YOLANDA
Director:CARRERA PÉREZ, DAVID
Co-director:BERRAL GARCÍA, JOSEP LLUÍS
Mention:No mention
RELATED PUBLICATIONS
Adaptive prediction models for data center resources utilization estimation
Baig, S.; Iqbal, W.; Berral, J.; Erradi, A.; Carrera, D.
IEEE transactions on network and service management, ISSN: 1932-4537 (JCR Impact Factor-2019: 3.878; Quartil: Q1)
Publication date: 12/2019
Journal article

Real-time data center's telemetry reduction and reconstruction using Markov chain models
Baig, S.; Iqbal, W.; Berral, J.; Erradi, A.; Carrera, D.
IEEE systems journal, ISSN: 1932-8184 (JCR Impact Factor-2019: 3.987; Quartil: Q1)
Publication date: 12/2019
Journal article

Adaptive sliding windows for improved estimation of data center resource utilization
Baig, S.; Iqbal, W.; Berral, J.; Carrera, D.
Future generation computer systems, ISSN: 0167-739X (JCR Impact Factor-2020: 7.187; Quartil: Q1)
Publication date: 03/2020
Journal article

Automatic distributed deep learning using resource-constrained edge devices
Gutierrez-Torre, A.; Bahadori, K.; Baig, S.; Iqbal, W.; Vardanega, T.; Berral, J.; Carrera, D.
IEEE internet of things journal, ISSN: 2327-4662 (JCR Impact Factor-2019: 9.936; Quartil: Q1)
Publication date: 2021
Journal article

AUTHOR:GARRIDO PLATERO, LUIS ANGEL
Title:Virtualization techniques for memory resource exploitation
Reading date:26/11/2019
Director:CARPENTER, PAUL MATTHEW
Co-director:BADIA SALA, ROSA MARIA
Mention:No mention
RELATED PUBLICATIONS
Continuous-action reinforcement learning for memory allocation in virtualized servers
International Conference on High Performance Computing 2019
Presentation date: 06/2019
Presentation of work at congresses

SmarTmem: Intelligent management of transcendent memory in a virtualized server
33rd International Parallel and Distributed Processing Symposium Workshops
Presentation date: 05/2019
Presentation of work at congresses

AUTHOR:VILLALBA NAVARRO, ÁLVARO
Title:Scalable processing of aggregate functions for data streams in resource-constrained environments
Reading date:05/09/2019
Director:CARRERA PÉREZ, DAVID
Mention:No mention
RELATED PUBLICATIONS
Multi-tenant Pub/Sub processing for real-time data streams
24th International European Conference on Parallel and Distributed Computing
Presentation date: 08/2018
Presentation of work at congresses

Constant-time approximate sliding window framework with error control
22nd IEEE International Symposium on Real-Time Distributed Computing
Presentation date: 05/2019
Presentation of work at congresses

AUTHOR:JAULMES, LUC ÉTIENNE
Title:Exploiting task-based programming models for resilience
Reading date:21/06/2019
Director:CASAS GUIX, MARC
Co-director:MORETÓ PLANAS, MIQUEL
Mention:International Mention
RELATED PUBLICATIONS
A vulnerability factor for ECC-protected memory
25th IEEE International Symposium on On-Line Testing and Robust System Design
Presentation date: 07/2019
Presentation of work at congresses

Runtime-guided ECC protection using online estimation of memory vulnerability
2020 International Conference for High Performance Computing, Networking, Storage and Analysis
Presentation date: 11/2020
Presentation of work at congresses

AUTHOR:RUMIPAMBA ZAMBRANO, RUBÉN DARÍO
Title:Contributions to network planning and operation of Flex-Grid/SDM optical core networks
Reading date:14/03/2019
Director:PERELLO MUNTAN, JORDI
Co-director:SPADARO, SALVATORE
Mention:No mention
RELATED PUBLICATIONS
Greenfield gradual migration planning toward spectrally-spatially flexible optical networks
Lechowicz, P.; Goscien, R.; Rumipamba, R.; Perello, J.; Spadaro, S.; Walkowiak, K.
IEEE communications magazine, ISSN: 0163-6804 (JCR Impact Factor-2019: 11.052; Quartil: Q1)
Publication date: 01/10/2019
Journal article

Design and assessment of FM-MCFs-suited SDM-ROADMs with versatile spatial group configurations and unified QoT estimator
Rumipamba, R.; Muñoz, R.; Casellas Regi, Ramon; Perello, J.; Spadaro, S.; Elfiqi, A.
Journal of lightwave technology, ISSN: 0733-8724 (JCR Impact Factor-2020: 4.142; Quartil: Q1)
Publication date: 15/11/2020
Journal article

AUTHOR:SERRANO GRACIA, MARÍA ASTÓN
Title:A time-predictable parallel programing model for real-time systems
Reading date:13/03/2019
Tutor/a:MARTORELL BOFILL, XAVIER
Director:QUIÑONES MORENO, EDUARDO
Mention:International Mention
RELATED PUBLICATIONS
Predictable parallel programming with OpenMP
Serrano, M.; Royuela, S.; Marongiu, A.; Quiñones, E.
River Publishers
Publication date: 2018
Book chapter

Towards an OpenMP specification for critical real-time systems
14th International Workshop on OpenMP
Presentation date: 09/2018
Presentation of work at congresses

Response-time analysis of DAG tasks supporting heterogeneous computing
55rd Design Automation Conference
Presentation date: 06/2018
Presentation of work at congresses

AUTHOR:SHARIATI, MOHAMMAD BEHNAM
Title:Design, monitoring and performance evaluation of high capacity optical networks
Reading date:22/02/2019
Director:VELASCO ESTEBAN, LUIS DOMINGO
Co-director:COMELLAS COLOME, JAUME
Mention:International Mention
RELATED PUBLICATIONS
Real-time optical spectrum monitoring in filterless optical metro networks
Shariati, M.; Ruiz, M.; Fresi, F.; Sgambelluri, A.; Cugini, F.; Velasco, L.
Photonic network communications, ISSN: 1387-974X (JCR Impact Factor-2020: 2.028; Quartil: Q3)
Publication date: 17/06/2020
Journal article

QoT-aware performance evaluation of spectrally-spatially flexible optical networks over FM-MCFs
Arpanaei, F.; Ardalani, N.; Beyranvand, H.; Shariati, M.
Journal of optical communications and networking, ISSN: 1943-0620 (JCR Impact Factor-2020: 3.984; Quartil: Q1)
Publication date: 01/08/2020
Journal article

Predictive autonomic transmission for low-cost low-margin metro optical networks
Ruiz, M.; Boitier, F.; Shariati, M.; Layec, P.; Velasco, L.
Photonic network communications, ISSN: 1387-974X (JCR Impact Factor-2020: 2.028; Quartil: Q3)
Publication date: 10/2020
Journal article

Feature-based optical spectrum monitoring for failure detection and identification
21st International Conference on Transparent Optical Networks
Presentation date: 10/07/2019
Presentation of work at congresses

AUTHOR:SALAMI, BEHZAD
Title:Aggressive undervolting of FPGAs: power & reliability trade-offs
Reading date:19/11/2018
Director:CRISTAL KESTELMAN, ADRIAN
Co-director:UNSAL, OSMAN SABRI
Mention:International Mention
RELATED PUBLICATIONS
Hardware acceleration for query processing: Leveraging FPGAs, CPUs, and memory
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Computing in science and engineering, ISSN: 1521-9615 (JCR Impact Factor-2019: 3.2
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Exceeding conservative limits: A consolidated analysis on modern hardware margins
Papadimitriou, G.; Chatzidimitriou, A.; Gizopoulos, D.; Reddi, V.; Leng, J.; Salami, B.; Unsal, O.; Cristal, A.
IEEE transactions on device and materials reliability, ISSN: 1530-4388 (JCR Impact Factor-2020: 1.761; Quartil: Q3)
Publication date: 06/2020
Journal article

A demo of FPGA aggressive voltage downscaling: power and reliability tradeoffs
28th International Conference on Field Programmable Logic and Applications
Presentation date: 08/2018
Presentation of work at congresses

Fault characterization through FPGA undervolting
28th International Conference on Field Programmable Logic and Applications
Presentation date: 08/2018
Presentation of work at congresses

Evaluating built-in ECC of FPGA on-chip memories for the mitigation of undervolting faults
27th Euromicro International Conference on Parallel, Distributed, and Network
Presentation date: 02/2019
Presentation of work at congresses

Modern hardware margins: CPUs, GPUs, FPGAs: recent system-level studies
25th IEEE International Symposium on On-Line Testing and Robust System Design
Presentation date: 07/2019
Presentation of work at congresses

A novel FPGA-based high throughput accelerator for binary search trees
17th International Conference on High Performance Computing and Simulation
Presentation date: 07/2019
Presentation of work at congresses

On the resilience of deep learning for reduced-voltage FPGAs
28th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
Presentation date: 03/2020
Presentation of work at congresses

LEGaTO: Low-energy, secure, and resilient toolset for heterogeneous computing
23rd Design, Automation and Test in Europe Conference and Exhibition
Presentation date: 03/2020
Presentation of work at congresses

An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration
50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Presentation date: 07/2020
Presentation of work at congresses

Demonstrating reduced-voltage FPGA-based neural network acceleration for power-efficiency
30th International Conference on Field-Programmable Logic and Applications
Presentation date: 09/2020
Presentation of work at congresses

Research projects

START DATEEND DATEACTIVITYFINANCING ENTITY
01/06/202031/05/2024UPC-Computación de Altas Prestaciones VIIIAGENCIA ESTATAL DE INVESTIGACION
01/06/202031/05/2023Sistemas informáticos y de red descentralizados con recursos distribuidosAGENCIA ESTATAL DE INVESTIGACION
13/05/202007/05/2021Subcontratación de servicios de Coordinación, Gestión y Dirección de un plan de formación en materia de Ciberseguridad para l’Agència de Ciberseguretat de Catalunya y la dinamización de la formación oEVERIS BPO, SLU
01/05/202001/11/2022A Unified Integrated Remain Well Clear Concept in Airspace D-G Class- URCLeaEDCommission of European Communities
14/04/202014/04/2020Merging level cache and data cache units having indicator bits related to speculative execution
01/04/202031/03/2023PROCESAMIENTO DE FLUJO DISTRIBUIDO EN SISTEMAS DE NIEBLA Y BORDE MEDIANTE COMPUTACIÓN TRANSPRECISAAGENCIA ESTATAL DE INVESTIGACION
01/04/202031/03/2023Marco de asignación de recursos holístico y fundacional para servicios edge computing optimizados y con alto impactoAGENCIA ESTATAL DE INVESTIGACION
07/01/202007/01/2020Disabling cache portions during low voltage operations - third continuation
01/01/202030/06/2020EU-US collaboration on NGI - NGI Explorers ProgramCommission of European Communities
01/01/202031/12/2020Research and Development Project with HuaweiHUAWEI TECHNOLOGIES Co
01/01/202031/12/2020Living lab e-micromobilityEUROPEAN INST OF INNOV.& TECHNOL.
01/01/202031/12/2020InnovaCity 2.0EUROPEAN INST OF INNOV.& TECHNOL.
01/01/202031/12/2021Construcció, gestió,manteniment DRONELABAJUNTAMENT CASTELLDEFELS
01/01/202031/12/2022Monitorización IoT de la calidad del aireAGENCIA ESTATAL DE INVESTIGACION
13/11/201931/12/2020FOOXY - COLLIDER 2019FUNDACIO BARCELONA MOBILE WORLD CAP
01/11/201930/04/2020Fast virtual SoC for advanced GPS algorithm evaluationGENT UNIVERSITEIT
30/10/201931/10/2020Preparar y dar soporte a las pruebas remotas de interoperabilidad basados en diferentes estándares de ETSI. Mantener herramientas de comprobación de conformidad de formatos de firmas digitales respectETSI
01/09/201931/08/2024CoCoUnit: An Energy-Efficient Processing Unit for Cognitive ComputingCommission of European Communities
01/08/201931/07/2022Research on an architecture/solution for BGP security and the overall problem of and Inter-Domain Routing securityHUAWEI TECHNOLOGIES Co
04/07/201903/07/2020decentraLizEd Data Governance for nExt geneRation internetCommission of European Communities
26/06/201926/07/2019Desenvolupament prova de concepte d'arquitectura BIG DATAFUNDACIÓ i2CAT
01/06/201931/05/2021TRaceo y ACompañamiento en el viaje con medios ITAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2021Inteligencia Artificial aplicada a Grafos para Redes Biológicas y de ComunicacionesAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2021Prestación de servicios de confianza en nubes periféricos descentralizadas para múltiples entornosAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2021Economía participativa para una plataforma computacional comunitaria descentralizadaAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2021Resiliencia Unificada para Sistemas InformáticosAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2022001-P-001723_Disseny d'acceleradors basats en la tecnologia RISC per a la propera generació de computadors (DRAC)GENCAT - DEPT. D'EMPRESA I OCUPACIO
24/04/201923/04/2022EUROCONTROL -PHDEUROCONTROL AGENCY
19/03/201931/07/2020Mejora de la infraestructura científico-técnica del Departamento de Arquitectura de Computadores de la UPCMinisterio de Ciencia e Innovación
20/02/201920/02/2020Networking Query Language for Mapping Services in Overlay NetworksSILICON VALLEY COMMUNITY FOUNDATION
01/01/201931/12/2022REAL-time monitoring and mitigation of nonlinearCommission of European Communities
01/01/201931/12/2021Gestión de una arquitectura jerárquica Fog-to-cloud para escenarios IoT: Compartición de recursosAGENCIA ESTATAL DE INVESTIGACION
01/01/201931/12/2022Integración de los objetivos para el desarrollo sostenible en la formación en sostenibilidad de las titulaciones universitarias españolasAGENCIA ESTATAL DE INVESTIGACION
01/01/201931/12/2020Supporting and maintaining the Trusted List Conformance Checker. This includes: fixing identified bugs; updating the tol to match requirements of updated revisions of ETSI TS 119 612; and add the capaETSI
01/01/201931/12/2020Drone research laboratory for the integration of mobile communicationsAGENCIA ESTATAL DE INVESTIGACION
22/11/201830/04/2019Conveni de col.laboració en Innovació en CiberseguretatFUNDACIÓ i2CAT
04/10/201829/02/2020STF-560: estándares que definan sintaxis estructurada para políticas de firma electrónica y acciones encaminadas a conseguir la aceptación de los servicios fiables europeos más allá de la UE.ETSI
20/09/201831/12/2019Gift funding to support the research on Network Twin System Modeling for Progressive ComputingFUTUREWEI TECHNOLOGIES INC.
17/07/201801/07/2020Col·laboració per promoure la innovació en els serveis TIC dels diferents àmbits d'acció pública i privada.SBS SEIDOR, S.L.
11/07/201811/07/2018Open Overlay Router
03/07/201803/07/2018Propagating a Prefetching Profile Bit from a Prefetch Queue to a Data Cache to Indicate that a Line Was Prefetched in Response to an Instruction within a Code Region
01/05/201830/04/2021REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systemsEuropean Commission
08/04/201808/04/2018Utilization of Register Checkpointing Mechanism with Pointer Swapping to Resolve Multithreading Mis-speculations
01/03/201831/12/2018Blockchain-based community networksAmmbrTech SCRL
01/03/201828/02/2022Ajut per a contractació RYC-2016-21104AGENCIA ESTATAL DE INVESTIGACION
01/03/201830/09/2018FEDERATION FOR FUTURE RESEARCH EXPERIMENTATION PLUSCommission of European Communities
26/01/201825/01/2019Intelligent routing based on traffic preHUAWEI TECHNOLOGIES CO. LTD
08/01/201831/12/2020Nuevos mecanismos inteligentes para medidas activas y pasivas de red en entornos multiconectadosAGENCIA ESTATAL DE INVESTIGACION
01/01/201831/12/2020Diseñando una infraestructura de red 5G definida mediante conocimiento hacia la próxima sociedad digitalAGENCIA ESTATAL DE INVESTIGACION
01/01/201831/12/2020Gestión y Análisis de Datos ComplejosAGENCIA ESTATAL DE INVESTIGACION
01/01/201831/12/2020CogniTive 5G application-aware optical metro netWorks Integrating moNitoring, data analyticS and optimizationAGENCIA ESTATAL DE INVESTIGACION
01/01/201831/12/2020Arquitectura de Computadors d'Altes PrestacionsAgència de Gestió d'Ajuts Universitaris i de Recerca (Agaur)
13/12/201714/06/2021Open Data based real-time urban mobility for car fleetsAGAUR. Agència de Gestió d'Ajuts Universitaris i de Recerca
13/11/201713/11/2017A METHOD AND COMPUTER PROGRAMS FOR IDENTIFYING VIDEO STREAMING QOE FROM NETWORK TRAFFIC
01/10/201730/09/2018CPU Steal Time in Linux Container Based InfrastructuresAmazon Web Services Inc.
25/09/201701/11/2019Concepción y coordinación del desarrollo de un sistema Big DataINTELLIGENT CLIENT DATA SERVICES SL
25/09/201701/11/2019Plataforma on-line tratam BigDataINTELLIGENT CLIENT DATA SERVICES SL
01/09/201731/08/2021Technology Transfer via Multinational Application ExperimentsCommission of European Communities
01/09/201730/11/2019Concept of Operations for EuRopean UTM SystemsCommission of European Communities
01/09/201730/09/2020My Travel CompanionCommission of European Communities
24/07/201724/07/2018Network Machine Learning: High-Value UseHUAWEI TECHNOLOGIES CO. LTD
10/07/201710/07/2017Sistema y procedimiento para el control a la adherencia de tratamientos médicos
13/06/201713/06/2017Disabling cache portions during low voltage operations - second continuation
01/06/201730/06/2020End-to-End Cognitive Network Slicing and Slice Management Framework in Virtualised Multi-Domain, Multi-Tenant 5G NetworksCommission of European Communities
01/06/201731/05/2020METRO High bandwidth, 5G Application-aware optical network, with edge storage,Commission of European Communities
01/06/201731/12/2020Performance evaluation of the Staflow SystemSTARFLOW, S.L.
29/05/201729/05/2017Managing task dependency
18/05/201717/07/2017Desenvolupament d'un frontend basat en tecnologia web i un interface amb una plataforma d'anàlisi de dades basada en web services en l'àmbit del màrqueting i publicitatESPACIO INVERSOR 5000, SL
01/05/201731/10/2017Federated Interoperable Semantic IoT/cloud Testbeds and ApplicationsCommission of European Communities
01/03/201731/10/2019Encapsulado de herramientas virtual para una gestión robusta de la heterogeneidad entre capas en sistemas ciberfísicos complejosAGENCIA ESTATAL DE INVESTIGACION
08/02/201731/12/2020C-ROADS SPAINCommission of European Communities
05/01/201728/02/2019RPAS-CAFEEUROCONTROL AGENCY
01/01/201730/06/2020VisorSurf - A Hardware Platform for Software-driven Functional MetasurfacesCommission of European Communities
01/01/201731/12/2019Lightweight Computation for Networks at the EdgeCommission of European Communities
01/01/201731/12/2019Towards an Open, Secure, Decentralized and Coordinated Fog-to-Cloud Management EcosystemCommission of European Communities
01/01/201731/12/2021ICREA ACADEMIA 2016-02INSTITUCIO CAT DE RECERCA I
01/01/201731/12/2018TRUst-Enhancing certified Solutions for SEcurity and protection of Citizens’ rights in digital EuropeCommission of European Communities
01/01/201731/12/2018PROGRAMAS DE FORMACIÓN PROFESIONAL EN CIBERSEGURIDAD VIVETFUNDACION APWG EUROPEAN UNION FOUND
01/01/201730/09/2019Mi compañero de viajeAGENCIA ESTATAL DE INVESTIGACION
01/01/201731/12/2018Redes comunitarias en regiones en desarolloAGENCIA ESTATAL DE INVESTIGACION
01/01/201731/12/2019Marco de servicios modulares para provisión de servicios IoT locales en entornos múltiplesAGENCIA ESTATAL DE INVESTIGACION
01/01/201731/12/2019(TIN2016-76635-C2-1-R) Arquitectura y programación de computadores escalables de alto rendimiento y bajo consumo (APCE)CICYT. MINISTERIO DE ECONOMÍA, INDUSTRIA Y COMPETITIVIDAD (MINECO). AEI. FEDER
30/12/201629/12/2019Integración Semántica de datos de IoT y su uso en la gestión energética de las Smart Grids y Smart CitiesMIN DE ECONOMIA Y COMPETITIVIDAD
30/12/201629/12/2019Operaciones de vuelo para múltiples aviones remotamente pilotadosMIN DE ECONOMIA Y COMPETITIVIDAD
30/12/201629/12/2020Arquitectura de Sistemas de Computación Inteligentes, UbicuosMIN DE ECONOMIA Y COMPETITIVIDAD
30/12/201629/12/2019Redes y Cloud comunitariosMIN DE ECONOMIA Y COMPETITIVIDAD
28/11/201601/02/2019STF-524: Desarrollo de estándares europeos de validación y firma electrónica sobre identificación y servicios fiables para transacciones electrónicas (según Reglamento EU No 910/2014)ETSI
28/11/201631/08/2018'Specialist Task Force' (STF) 524 on Standards for eIDAS trust services including electronic signatures Í trust services for signature validation.Comisión Europea
15/11/201614/11/2017Extending Hybrid Cloud Towards EdgeIBM RESEARCH
01/11/201631/10/2018Criminal Justice Access to Digital Evidences in the Cloud - LIVE_FORensicsEUR COM DG JUSTICE AND CONSUMERS
01/11/201631/10/2019Combining guaranteed minimum income and active social policies in deprived urban areas of BarcelonaCommission of European Communities
31/10/201628/02/2019STF-523: Desarrollo de estándares europeos para soportar la prestación de servicios fiables de entrega electrónica certificadaETSI
31/10/201628/02/2019Specialist Task Force STF 523 (TC ESI) Standards for eIDAS trust services – electronic registered delivery and registered electronic mailComisión Europea
21/10/201621/10/2016Accessing data stored in a database system
20/10/201631/12/2016Plugtest ASiC 2016: Tareas de soporte a la preparación, conducción y posterior informe de un evento de interoperabilidadETSI
01/10/201631/10/2018Fast Data-Path Open Overlays (FD.io/OOR)SILICON VALLEY COMMUNITY FOUNDATION
01/09/201631/12/2017Programa d'APS de la UPC per donar suport TIC a les entitats socialsAjuntament de Barcelona
29/07/201628/01/2020Anàlisi i optimització d'infraestructures de xarxa i serveis digitals de comunsAGAUR. Agència de Gestió d'Ajuts Universitaris i de Recerca
01/06/201631/12/2018Actualización y mantenimiento del comprobador de conformidad de las listas de prestatarios de servicios fiablesETSI
23/05/201622/05/2017LG-BSC contract 2016LG Mobile
09/05/201608/05/2018Assessment of Performance in current ATM operations and of new Concepts of operations for its Holistic EnhancementCommission of European Communities
01/05/201630/04/2019Enhancing critical infraestructure protection with innovative security frameworkCommission of European Communities
27/04/201627/10/2018Cloud-based Monitoring Service for Software Defined Networks (Phase 2)Comissió Europea
01/04/201631/03/2018Wake vortex simulation and analysis to enhance en-route separation management in EuropeCommission of European Communities
01/04/201630/05/2016eSigPlugtest 2016ETSI
01/04/201631/03/2020Lenovo BSC Master Collaboration Agreement 2015Lenovo Spain SL
01/03/201631/12/2019IBM-BSC Deep Learning CentreIBM
29/01/201631/12/2016Adecuación herramientas seguridad en puesto de trabajo y entornos móvilesMNEMO EVOLUT. & INTEGRATION SERV SA
01/01/201631/03/2019Collective Awareness Platform for Tropospheric OzoneCommission of European Communities
01/01/201631/12/2018Network Infraestructure as CommonsCommission of European Communities
01/01/201631/12/2019Secure GENomic information COMpressionMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201631/12/2020Computación de altas prestaciones VIIMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201631/12/2018Gestión de una arquitectura cloud jerárquica para escenarios IoT: Fogging cloudMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201630/06/2019Educación e innovación social para la sostenibilidad. Formación en las Universidades españolas de profesionales como agentes de cambio para afrontar los retos de la sociedad.MIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201631/12/2020ICREA ACADEMIA 2015-05INSTITUCIO CAT DE RECERCA I
01/01/201631/12/2019Evaluación de código abierto de herramientas para la generación y validación de firmas AdES y de edición de listas de prestatarios de servicios de certificación en estados miembros de la UESEALED s.p.r.l.
01/01/201631/12/2019BSC Severo Ochoa Program 2MINECO. Secretaria de Estado de Investigación, Desarrollo e Innovación.
01/01/201628/02/2018687698 - HIPEAC 4 - European Network of Excellence on HighPerformance Embedded Architecture and CompilersEuropean Horizon 2020. Funding scheme: CSA - Coordination & Support Action. Topic: ICT-04-2015
01/01/201631/12/2019Computacion de Altas Prestaciones VIIMINECO. Secretaria de Estado de Investigación, Desarrollo e Innovación.
19/11/201518/05/2019Definition of new WAN paradigms enabled by MPTCP technologyAGAUR. Agència de Gestió d'Ajuts Universitaris i de Recerca
01/11/201531/10/2016Open DPDK encapsulation (LISP, VXAN and GPE): performance and optimizationSILICON VALLEY COMMUNITY FOUNDATION
01/10/201531/12/2016Programa Pilot d’Aprenentatge-Servei de la UPC, suport TIC Entitats SocialsAjuntament de Barcelona
01/10/201530/09/2016IEEE Simposio Internacional en Arquitecturas de Alto RendimientoMIN DE ECONOMIA Y COMPETITIVIDAD
01/10/201530/09/2017Elastics Networks: Nuevos paradigmas de Redes Elásticas para un mundo radicalmente basado en Cloud y Fog ComputingUniversitat Politècnica de Catalunya
01/09/201531/08/2019HACIA LAS COMUNICACIONES RF BASADAS EN GRAFENO DEMOSTRANDO LAS ANTENAS DE GRAFENOMIN DE ECONOMIA Y COMPETITIVIDAD
01/09/201531/12/2016VolTIC 2015Ajuntament de Barcelona
26/08/201526/08/2015Support for Speculative Ownership without Data - continuation
19/08/201518/08/2017Next Generation Drone-Based Spectral Systems for Environmental MonitorinUNIVERSITY CORPORATION
05/08/201530/11/2015XAdES Plugtest 2015ETSI
25/07/201531/01/2016Tender MARKT/2014/039/E. Análisis/'black box/' de herramientas de generación y validación de firmas electrónicas acordes a los perfiles básicos estandarizados por ETSI.SEALED s.p.r.l.
15/06/201514/10/2015Experimentation with Network Polygraph in the Fed4FIRE testbed (POLYTEST)Comissió Europea
11/06/201531/12/2015Ampliació de la xarxa Wifi a l'escola i formació dels professors en eines educatives TIC i manteniment del recursos, Pikine-Dakar, SenegalCentre de Cooperació per al Desenvolupament , UPC
11/06/201531/12/2015Seminari i desplegament d’una xarxa mesh comunitaria sense fil per educació i recerca al Mekele Institute of Technology, EtiòpiaCentre de Cooperació per al Desenvolupament , UPC
02/06/201502/06/2015Frequency and Voltage Scaling Architecture - Continuation
01/06/201531/05/2017Coordinating European Research on Molecular CommunicationsCommission of European Communities
18/05/201530/04/2016Multilayer IP/WDM Planning Algorithms for WAN Automation (WAE)CISCO SYSTEMS
01/05/201501/11/2018Information technologies for shift to railCommission of European Communities
01/05/201530/04/2016Acuerdo con RED.ES para la colaboración de la UPC en el proyecto europeo/'Multi-Gigabit European research and Education Network and Associated Services - GN4/'RED.ES
01/05/201530/04/2016GN4-1 Research and Education Networking - GÉANTCommission of European Communities
15/04/201530/08/2015Tareaas de soporte a la preparación, conducción y posterior informe de un evento de interoperabilidad sobre firmas electronicas CAdES.ETSI
14/04/201530/11/2015Assessorament i intercanvis d'informació en smart cities i internet of thingsBCN.SUPERCOMPUTING CENTER
01/04/201531/10/2015Cloud-based Visibility Service for Software Defined Networks (Phase 1)Comisión Europea
15/03/201530/06/2015PAdES Plugtest 2015ETSI
02/03/201502/03/2015Multipath Provisioning of L4-L7 Traffic in a Network
01/03/201530/06/2015Curso de Gestión de Proyectos InformáticosSIEMENS HEALTHCARE DIAGNOSTICS,S.L.
01/03/201528/02/2016Collective enHanced Environment for Social TasksCommission of European Communities
01/02/201531/01/2018AXIOMComisión Europea
01/02/201531/01/2016CrowdFIEMIN DE ECONOMIA Y COMPETITIVIDAD
27/01/201530/04/2015Grant to support the TMA PhD School 2015ACM-SIGCOMM
14/01/201513/01/2018Use of graph databases in industrial environmentsAGAUR. Agència de Gestió d'Ajuts Universitaris i de Recerca
01/01/201531/12/2017Service-oriented hybrid optical network and cloud infrastructure featuring high throughput and ultra-low latencyMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201531/12/2017Infraestructura de Red Sostenible para la Futura Sociedad DigitalMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201531/12/2015Plataforma Conciencia Colectiva para la contaminación por ozono troposféricoMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201530/06/2016TECCIT15-1-0010: Pla d'Actuació en transferència tecnològica 2015 (DAMA)ACC10
01/01/201531/12/2018Computación de Altas Prestaciones VIIMinisterio de Ciencia e Innovación
01/01/201530/06/2016Support IT solution for creative fashion designers by integrated software systems to collect, define and visualize textile and clothing trends through innovative image analysis from open dataCommission of European Communities
27/06/201313/11/2017Contracte de transferència de tecnologia Talaia Networks, S.L.Talaia Networks, S.L.

Teaching staff and research groups

Teachers

Doctoral Programme teachers:Other teachers linked to the Doctoral Programme:

Research projects

START DATEEND DATEACTIVITYFINANCING ENTITY
01/06/202031/05/2024UPC-Computación de Altas Prestaciones VIIIAGENCIA ESTATAL DE INVESTIGACION
01/06/202031/05/2023Sistemas informáticos y de red descentralizados con recursos distribuidosAGENCIA ESTATAL DE INVESTIGACION
13/05/202007/05/2021Subcontratación de servicios de Coordinación, Gestión y Dirección de un plan de formación en materia de Ciberseguridad para l’Agència de Ciberseguretat de Catalunya y la dinamización de la formación oEVERIS BPO, SLU
01/05/202001/11/2022A Unified Integrated Remain Well Clear Concept in Airspace D-G Class- URCLeaEDCommission of European Communities
14/04/202014/04/2020Merging level cache and data cache units having indicator bits related to speculative execution
01/04/202031/03/2023PROCESAMIENTO DE FLUJO DISTRIBUIDO EN SISTEMAS DE NIEBLA Y BORDE MEDIANTE COMPUTACIÓN TRANSPRECISAAGENCIA ESTATAL DE INVESTIGACION
01/04/202031/03/2023Marco de asignación de recursos holístico y fundacional para servicios edge computing optimizados y con alto impactoAGENCIA ESTATAL DE INVESTIGACION
07/01/202007/01/2020Disabling cache portions during low voltage operations - third continuation
01/01/202030/06/2020EU-US collaboration on NGI - NGI Explorers ProgramCommission of European Communities
01/01/202031/12/2020Research and Development Project with HuaweiHUAWEI TECHNOLOGIES Co
01/01/202031/12/2020Living lab e-micromobilityEUROPEAN INST OF INNOV.& TECHNOL.
01/01/202031/12/2020InnovaCity 2.0EUROPEAN INST OF INNOV.& TECHNOL.
01/01/202031/12/2021Construcció, gestió,manteniment DRONELABAJUNTAMENT CASTELLDEFELS
01/01/202031/12/2022Monitorización IoT de la calidad del aireAGENCIA ESTATAL DE INVESTIGACION
13/11/201931/12/2020FOOXY - COLLIDER 2019FUNDACIO BARCELONA MOBILE WORLD CAP
01/11/201930/04/2020Fast virtual SoC for advanced GPS algorithm evaluationGENT UNIVERSITEIT
30/10/201931/10/2020Preparar y dar soporte a las pruebas remotas de interoperabilidad basados en diferentes estándares de ETSI. Mantener herramientas de comprobación de conformidad de formatos de firmas digitales respectETSI
01/09/201931/08/2024CoCoUnit: An Energy-Efficient Processing Unit for Cognitive ComputingCommission of European Communities
01/08/201931/07/2022Research on an architecture/solution for BGP security and the overall problem of and Inter-Domain Routing securityHUAWEI TECHNOLOGIES Co
04/07/201903/07/2020decentraLizEd Data Governance for nExt geneRation internetCommission of European Communities
26/06/201926/07/2019Desenvolupament prova de concepte d'arquitectura BIG DATAFUNDACIÓ i2CAT
01/06/201931/05/2021TRaceo y ACompañamiento en el viaje con medios ITAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2021Inteligencia Artificial aplicada a Grafos para Redes Biológicas y de ComunicacionesAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2021Prestación de servicios de confianza en nubes periféricos descentralizadas para múltiples entornosAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2021Economía participativa para una plataforma computacional comunitaria descentralizadaAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2021Resiliencia Unificada para Sistemas InformáticosAGENCIA ESTATAL DE INVESTIGACION
01/06/201931/05/2022001-P-001723_Disseny d'acceleradors basats en la tecnologia RISC per a la propera generació de computadors (DRAC)GENCAT - DEPT. D'EMPRESA I OCUPACIO
24/04/201923/04/2022EUROCONTROL -PHDEUROCONTROL AGENCY
19/03/201931/07/2020Mejora de la infraestructura científico-técnica del Departamento de Arquitectura de Computadores de la UPCMinisterio de Ciencia e Innovación
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01/01/201931/12/2022REAL-time monitoring and mitigation of nonlinearCommission of European Communities
01/01/201931/12/2021Gestión de una arquitectura jerárquica Fog-to-cloud para escenarios IoT: Compartición de recursosAGENCIA ESTATAL DE INVESTIGACION
01/01/201931/12/2022Integración de los objetivos para el desarrollo sostenible en la formación en sostenibilidad de las titulaciones universitarias españolasAGENCIA ESTATAL DE INVESTIGACION
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01/01/201931/12/2020Drone research laboratory for the integration of mobile communicationsAGENCIA ESTATAL DE INVESTIGACION
22/11/201830/04/2019Conveni de col.laboració en Innovació en CiberseguretatFUNDACIÓ i2CAT
04/10/201829/02/2020STF-560: estándares que definan sintaxis estructurada para políticas de firma electrónica y acciones encaminadas a conseguir la aceptación de los servicios fiables europeos más allá de la UE.ETSI
20/09/201831/12/2019Gift funding to support the research on Network Twin System Modeling for Progressive ComputingFUTUREWEI TECHNOLOGIES INC.
17/07/201801/07/2020Col·laboració per promoure la innovació en els serveis TIC dels diferents àmbits d'acció pública i privada.SBS SEIDOR, S.L.
11/07/201811/07/2018Open Overlay Router
03/07/201803/07/2018Propagating a Prefetching Profile Bit from a Prefetch Queue to a Data Cache to Indicate that a Line Was Prefetched in Response to an Instruction within a Code Region
01/05/201830/04/2021REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systemsEuropean Commission
08/04/201808/04/2018Utilization of Register Checkpointing Mechanism with Pointer Swapping to Resolve Multithreading Mis-speculations
01/03/201831/12/2018Blockchain-based community networksAmmbrTech SCRL
01/03/201828/02/2022Ajut per a contractació RYC-2016-21104AGENCIA ESTATAL DE INVESTIGACION
01/03/201830/09/2018FEDERATION FOR FUTURE RESEARCH EXPERIMENTATION PLUSCommission of European Communities
26/01/201825/01/2019Intelligent routing based on traffic preHUAWEI TECHNOLOGIES CO. LTD
08/01/201831/12/2020Nuevos mecanismos inteligentes para medidas activas y pasivas de red en entornos multiconectadosAGENCIA ESTATAL DE INVESTIGACION
01/01/201831/12/2020Diseñando una infraestructura de red 5G definida mediante conocimiento hacia la próxima sociedad digitalAGENCIA ESTATAL DE INVESTIGACION
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13/12/201714/06/2021Open Data based real-time urban mobility for car fleetsAGAUR. Agència de Gestió d'Ajuts Universitaris i de Recerca
13/11/201713/11/2017A METHOD AND COMPUTER PROGRAMS FOR IDENTIFYING VIDEO STREAMING QOE FROM NETWORK TRAFFIC
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01/09/201730/09/2020My Travel CompanionCommission of European Communities
24/07/201724/07/2018Network Machine Learning: High-Value UseHUAWEI TECHNOLOGIES CO. LTD
10/07/201710/07/2017Sistema y procedimiento para el control a la adherencia de tratamientos médicos
13/06/201713/06/2017Disabling cache portions during low voltage operations - second continuation
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01/01/201731/12/2019Lightweight Computation for Networks at the EdgeCommission of European Communities
01/01/201731/12/2019Towards an Open, Secure, Decentralized and Coordinated Fog-to-Cloud Management EcosystemCommission of European Communities
01/01/201731/12/2021ICREA ACADEMIA 2016-02INSTITUCIO CAT DE RECERCA I
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01/01/201731/12/2018PROGRAMAS DE FORMACIÓN PROFESIONAL EN CIBERSEGURIDAD VIVETFUNDACION APWG EUROPEAN UNION FOUND
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30/12/201629/12/2019Operaciones de vuelo para múltiples aviones remotamente pilotadosMIN DE ECONOMIA Y COMPETITIVIDAD
30/12/201629/12/2020Arquitectura de Sistemas de Computación Inteligentes, UbicuosMIN DE ECONOMIA Y COMPETITIVIDAD
30/12/201629/12/2019Redes y Cloud comunitariosMIN DE ECONOMIA Y COMPETITIVIDAD
28/11/201601/02/2019STF-524: Desarrollo de estándares europeos de validación y firma electrónica sobre identificación y servicios fiables para transacciones electrónicas (según Reglamento EU No 910/2014)ETSI
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01/11/201631/10/2018Criminal Justice Access to Digital Evidences in the Cloud - LIVE_FORensicsEUR COM DG JUSTICE AND CONSUMERS
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31/10/201628/02/2019Specialist Task Force STF 523 (TC ESI) Standards for eIDAS trust services – electronic registered delivery and registered electronic mailComisión Europea
21/10/201621/10/2016Accessing data stored in a database system
20/10/201631/12/2016Plugtest ASiC 2016: Tareas de soporte a la preparación, conducción y posterior informe de un evento de interoperabilidadETSI
01/10/201631/10/2018Fast Data-Path Open Overlays (FD.io/OOR)SILICON VALLEY COMMUNITY FOUNDATION
01/09/201631/12/2017Programa d'APS de la UPC per donar suport TIC a les entitats socialsAjuntament de Barcelona
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01/06/201631/12/2018Actualización y mantenimiento del comprobador de conformidad de las listas de prestatarios de servicios fiablesETSI
23/05/201622/05/2017LG-BSC contract 2016LG Mobile
09/05/201608/05/2018Assessment of Performance in current ATM operations and of new Concepts of operations for its Holistic EnhancementCommission of European Communities
01/05/201630/04/2019Enhancing critical infraestructure protection with innovative security frameworkCommission of European Communities
27/04/201627/10/2018Cloud-based Monitoring Service for Software Defined Networks (Phase 2)Comissió Europea
01/04/201631/03/2018Wake vortex simulation and analysis to enhance en-route separation management in EuropeCommission of European Communities
01/04/201630/05/2016eSigPlugtest 2016ETSI
01/04/201631/03/2020Lenovo BSC Master Collaboration Agreement 2015Lenovo Spain SL
01/03/201631/12/2019IBM-BSC Deep Learning CentreIBM
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01/01/201631/03/2019Collective Awareness Platform for Tropospheric OzoneCommission of European Communities
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01/01/201631/12/2019Secure GENomic information COMpressionMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201631/12/2020Computación de altas prestaciones VIIMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201631/12/2018Gestión de una arquitectura cloud jerárquica para escenarios IoT: Fogging cloudMIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201630/06/2019Educación e innovación social para la sostenibilidad. Formación en las Universidades españolas de profesionales como agentes de cambio para afrontar los retos de la sociedad.MIN DE ECONOMIA Y COMPETITIVIDAD
01/01/201631/12/2020ICREA ACADEMIA 2015-05INSTITUCIO CAT DE RECERCA I
01/01/201631/12/2019Evaluación de código abierto de herramientas para la generación y validación de firmas AdES y de edición de listas de prestatarios de servicios de certificación en estados miembros de la UESEALED s.p.r.l.
01/01/201631/12/2019BSC Severo Ochoa Program 2MINECO. Secretaria de Estado de Investigación, Desarrollo e Innovación.
01/01/201628/02/2018687698 - HIPEAC 4 - European Network of Excellence on HighPerformance Embedded Architecture and CompilersEuropean Horizon 2020. Funding scheme: CSA - Coordination & Support Action. Topic: ICT-04-2015
01/01/201631/12/2019Computacion de Altas Prestaciones VIIMINECO. Secretaria de Estado de Investigación, Desarrollo e Innovación.
19/11/201518/05/2019Definition of new WAN paradigms enabled by MPTCP technologyAGAUR. Agència de Gestió d'Ajuts Universitaris i de Recerca
01/11/201531/10/2016Open DPDK encapsulation (LISP, VXAN and GPE): performance and optimizationSILICON VALLEY COMMUNITY FOUNDATION
01/10/201531/12/2016Programa Pilot d’Aprenentatge-Servei de la UPC, suport TIC Entitats SocialsAjuntament de Barcelona
01/10/201530/09/2016IEEE Simposio Internacional en Arquitecturas de Alto RendimientoMIN DE ECONOMIA Y COMPETITIVIDAD
01/10/201530/09/2017Elastics Networks: Nuevos paradigmas de Redes Elásticas para un mundo radicalmente basado en Cloud y Fog ComputingUniversitat Politècnica de Catalunya
01/09/201531/08/2019HACIA LAS COMUNICACIONES RF BASADAS EN GRAFENO DEMOSTRANDO LAS ANTENAS DE GRAFENOMIN DE ECONOMIA Y COMPETITIVIDAD
01/09/201531/12/2016VolTIC 2015Ajuntament de Barcelona
26/08/201526/08/2015Support for Speculative Ownership without Data - continuation
19/08/201518/08/2017Next Generation Drone-Based Spectral Systems for Environmental MonitorinUNIVERSITY CORPORATION
05/08/201530/11/2015XAdES Plugtest 2015ETSI
25/07/201531/01/2016Tender MARKT/2014/039/E. Análisis/'black box/' de herramientas de generación y validación de firmas electrónicas acordes a los perfiles básicos estandarizados por ETSI.SEALED s.p.r.l.
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11/06/201531/12/2015Seminari i desplegament d’una xarxa mesh comunitaria sense fil per educació i recerca al Mekele Institute of Technology, EtiòpiaCentre de Cooperació per al Desenvolupament , UPC
02/06/201502/06/2015Frequency and Voltage Scaling Architecture - Continuation
01/06/201531/05/2017Coordinating European Research on Molecular CommunicationsCommission of European Communities
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01/05/201530/04/2016GN4-1 Research and Education Networking - GÉANTCommission of European Communities
15/04/201530/08/2015Tareaas de soporte a la preparación, conducción y posterior informe de un evento de interoperabilidad sobre firmas electronicas CAdES.ETSI
14/04/201530/11/2015Assessorament i intercanvis d'informació en smart cities i internet of thingsBCN.SUPERCOMPUTING CENTER
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15/03/201530/06/2015PAdES Plugtest 2015ETSI
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01/02/201531/01/2016CrowdFIEMIN DE ECONOMIA Y COMPETITIVIDAD
27/01/201530/04/2015Grant to support the TMA PhD School 2015ACM-SIGCOMM
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01/01/201530/06/2016Support IT solution for creative fashion designers by integrated software systems to collect, define and visualize textile and clothing trends through innovative image analysis from open dataCommission of European Communities
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Quality

The Validation, Monitoring, Modification and Accreditation Framework (VSMA Framework) for official degrees ties the quality assurance processes (validation, monitoring, modification and accreditation) carried out over the lifetime of a course to two objectives—the goal of establishing coherent links between these processes, and that of achieving greater efficiency in their management—all with the overarching aim of improving programmes.

Validation

Monitoring

Accreditation

    Registry of Universities, Centers and Degrees (RUCT)

    Indicators

    Up