Committee:
     PRESIDENT: PEREZ, CHRISTIAN
     SECRETARI: CORBALAN GONZALEZ, JULITA
     VOCAL: PACHECO PAGES, ANDRES
Thesis abstract: The Large Hadron Collider (LHC) ALICE (A Large Ion Collider Experiment) experiment uses grid computing for its extensive data processing and analysis. The ALICE Grid is composed of 48 sites distributed globally, which provide access to over 300,000 CPU cores. This diverse environment presents unique challenges as the computing nodes are very heterogeneous in terms of hardware, resource availability and management policies. This thesis focuses on optimising resource utilisation and job execution within the ALICE Grid in the context of the evolving multicore computing paradigm. The transition from single to multicore slots, combined with the increasing prevalence of multiprocess and multithreaded workflows, requires new resource management approaches.The thesis presents a black-box analysis of the multicore experiment software framework, tracing resource usage and system calls. Multiple sources of overhead were identified, particularly concerning the large amount of short-lived processes spawned by some workflows. To address this, the JAliEn monitoring system was extended and improved to accurately account for the resource utilisation of these short-lived processes. The observations led to modifications on the internal job workflow, resulting in a 47% reduction in the number of deployed processes and a 35% decrease in overall job execution time.For tailoring job requests to the specific characteristics of the executing systems, a model is proposed to estimate job execution times. This model leverages proportionality factors from the execution times on different Grid CPU models and uses them to dynamically scale job requests.To ensure the coherent and controlled utilisation of CPU resources, two approaches are proposed. The first uses CPU pinning and adapts the core selection to the processor architecture, optimising resource allocation for specific workloads. The second uses cgroups v2 sub-partitioning features to set boundaries on job CPU utilisation. The thesis made significant contributions to popular grid batch systems by enabling support for cgroups v2. This integration allowed JAliEn to become the first grid middleware to make use of this powerful resource management technology.When a slot is sub-partitioned to run multiple jobs in parallel, careful resource orchestration is crucial. This thesis presents a module within JAliEn that ensures equitable memory resource distribution among co-executing jobs. This module implements a targeted preemption of resource-intensive jobs to prevent slot overconsumption and ensure that jobs remain within their allocated memory limits.The thesis explores whole-node slot allocations in which JAliEn manages all the resources of a node. This novel scheduling model offers great flexibility and adaptability. To maximise resource usage in whole-node slots, CPU oversubscription was introduced to allow the execution of additional jobs when the running workload does not fully use the available CPU resources. To exploit whole-node allocations and maximise resource utilisation, the thesis proposes the extension of job brokering to consider not only CPU availability but also memory and disk space. Furthermore, the job definition syntax was equipped with new parameters for users to have greater control over resource requests.To sum up, this thesis presents a set of contributions that have substantially improved the efficiency and performance of grid computing within the ALICE experiment. The thesis addresses the challenges emerging from the evolving multicore environment by optimising resource utilisation and improving middleware reliability and observability. All these contributions introduced significant advances to the capabilities of the ALICE Grid, effectively enabling a more efficient data analysis for the LHC experiment.

Committee:
     PRESIDENT: EECKHOUT, LIEVEN
     SECRETARI: CANAL CORRETGER, RAMON
     VOCAL: PAIVA CARDOSO, JOÃO MANUEL
Thesis abstract: Due to increasing concern about energy efficiency and the current trend to scale out HPC systems to many computing nodes, this thesis tries to tackle both problems with the help of hardware acceleration and programming models.Regarding the first topic, FPGAs have been the target of study due to their high flexibility to adapt to any computing workload and due to their high energy efficiency. We present extensions to the OmpSs@FPGA framework, which provides a high-level task-based programming interface to non-FPGA experts.These extensions include compiler directives to automatically optimize FPGA code, a hardware task scheduling runtime with dependence analysis called POM, and a multi-FPGA MPI-like API and runtime, called OMPIF.In addition, we present the Implicit Message Passing (IMP) model, which combines task-based and message-passing programming models, leveraging dependence information and a static data distribution.IMP automatically communicates data between nodes when required by the data dependencies of a task.Therefore, the user does not need to write any call to MPI or OMPIF in the code, as this is handled by IMP.We evaluate this model on both FPGA and CPU clusters, with hardware acceleration for task scheduling and message passing using the POM and OMPIF runtimes.For CPU clusters, we study several ways to incorporate POM into an SoC, first with an embedded FPGA, then we design it as an ASIC for a RISC-V core, and finally in an FPGA softcore also based on RISC-V.In the last case, we use both POM and OMPIF to evaluate distributed applications with a cluster of FPGAs that emulate a CPU cluster.We evaluate IMP and regular MPI+tasks programming with several benchmarks: Matrix Multiply, Spectra, N-body, Heat, and Cholesky.With the mentioned contributions, we achieve several objectives.First, we demonstrate that with OmpSs@FPGA we can achieve similar absolute performance to a CPU node for some benchmarks, like N-body, and outperform in energy efficiency to similar CPU and GPU architectures (in area and technology).Second, we also evaluate multi-FPGA applications on three different clusters: cloudFPGA, ESSPER, and MEEP, which have very distinct characteristics.With IMP, we show that we can scale linearly the N-body, Heat, and Cholesky benchmarks to 64 FPGAs.For CPUs, we are also able to scale linearly with the same benchmarks on an 8-core, 64-node cluster, with 512 cores in total.With our hardware-software co-design, which combines the hardware acceleration of task scheduling and message passing with IMP, we show a solution to accelerate HPC workloads as transparently as possible to the programmer, thus boosting productivity.This solution has been designed for heterogeneous systems based on FPGAs, but also based on CPUs.The latter also benefit significantly from the runtime overhead reduction thanks to the hardware acceleration.

Committee:
     PRESIDENT: NADIMI GOKI, PANTEA
     SECRETARI: BARZEGAR, SIMA
     VOCAL: GONÇALO SEQUEIRA, DIOGO
Thesis abstract: This thesis focuses on implementing more robust control and management strategies such as those based on machine learning to enhance intelligence and drive towards autonomous operation is crucial for the future of optical communications. In this regard, this thesis aims at three specific objectives: The first objective is to develop a multiband optical transmission simulator. It can be challenging to conduct simulations on a fully loaded MB system with hundreds of channels. In addition, in MB optical transmission, the Inter-channel Stimulated Raman Scattering (ISRS) becomes a major effect, which adds more complexity. In view of that, the Fourth Order Runge-Kutta in Interaction Picture (RK4IP) method is evaluated as an alternative to reduce time complexity, which is complemented with an adaptive step size algorithm to further reduce the computation time. We show that RK4IP provides an accuracy comparable to that of SSFM with reduced computation time, which enables its application for MB optical transmission simulation. The second objective focuses on developing models for C+L+S Multiband Optical Transmission System In this objective of this thesis, we focus on modelling MB optical transmission to provided fast and accurate QoT estimation and propose Machine Learning (ML) approaches based on neural networks, which can be easily integrated into an Optical Layer Digital Twin (DT) solution. We start by considering approaches that can be used for accurate signal propagation modelling. Even though solutions like the Splitstep Fourier method (SSFM) for solving the non-linear Schrödinger equation (NLSE) cannot be used for QoT estimation due to their very high time complexity. Therefore, ML modelling approaches are considered to be integrated in the OCATA DT, where models predict optical signal propagation in the time domain. Being able to predict the optical signal in the time domain, as it will be received after propagation, opens opportunities for automating network operation, including connection provisioning and failure management. The third objective of this thesis is to develop a semi-analytical model for measuring the gain profile of amplifiers in both fully loaded and partially loaded conditions of the metro- access network. The power imbalance is one of the issues associated with transitioning to a metro-access merged network. Additionally, maintaining these two separate networks (metro and access) is both complicated and costly. The node that interconnects the two networks must perform O-E-O conversions on the data traversing between them. The current network system uses ROADM in nodes, which is all optical and requires no O-E-O conversion. Therefore, this goal primarily focuses on characterizing the parameters of EDFA present in reconfigurable optical add-drop multiplexers (ROADMs) with the aim of achieving a balance between flexibility, complexity, and cost. These nodes must be thoroughly characterized regarding optical losses, power consumption, and other metrics. Once evaluated, the performance of these nodes can be modelled to enable the SDN controller to incorporate them into the network.

Committee:
     PRESIDENT: SECCI, STEFANO
     SECRETARI: DOMINGO PASCUAL, JORDI
     VOCAL: ANAGNOSTOPOULOS, MARIOS
Thesis abstract: Modern networks support critical applications with increasingly diverse, complex, and dynamic requirements. Ensuring their proper functioning is vital to maintaining the reliability and availability of these dependent services. Anomaly Detection (AD) plays a crucial role in preserving network performance by promptly identifying disruptions or degradations. In computer networks, the behavior of a node (e.g., a router) is heavily influenced by its surrounding elements. However, many traditional and Machine Learning (ML)-based methods often fail to exploit these structural correlations effectively, and in some cases ignore them entirely.While some existing approaches attempt to incorporate topological information into the AD task, they often do so suboptimally, losing key relational information. As a result, these systems struggle to achieve the robustness and adaptability required for deployment in dynamic, production environments.Graph Neural Networks (GNNs) have recently gained prominence for modeling tasks where spatial correlations are essential. Nevertheless, their application to AD in computer networks remains underexplored, despite their natural suitability for such structured environments. This thesis investigates new uses of GNNs for AD in networked systems, focusing on three representative scenarios: (i) Border Gateway Protocol (BGP) AD, where hijacks and misconfigurations cause structural changes; (ii) contextual AD, where anomalies depend on the behavior of neighboring entities; and (iii) zero-shot spatiotemporal modeling, enabling forecasting in data-scarce environments.In the first scenario, we leverage the raw BGP topology to design a model capable of generalizing across incidents while maintaining a low false-positive rate, an essential requirement for real-world deployment. We evaluate the model on well-known BGP incidents and extensive regular operation data to validate its robustness.For contextual AD, we propose two GNN-based models that uncover hidden relationships between flows in a backbone network. We validate these models on datasets containing both real and synthetic anomalies and show how the attention mechanisms provide interpretable visualizations of the learned contextual dependencies.Finally, we introduce a GNN-based spatiotemporal model trained on non-networking time series, capable of achieving zero-shot forecasting performance on network monitoring data. The model exploits attention mechanisms to learn and transfer spatial and temporal correlations across domains, outperforming state-of-the-art baselines. Moreover, the learned attention patterns suggest opportunities to simplify spatiotemporal representations, which is critical for scaling models to large production networks. These predictions can subsequently be used to perform AD, which is our main motivation to develop it.Collectively, the contributions of this thesis advance the use of Graph Neural Networks for Anomaly Detection in computer networks by systematically leveraging topological information to improve predictive performance and interpretability. Furthermore, the role of attention mechanisms for providing more interpretable results is also explored, opening the door to using them as a way to both understand the reasons behind the detected anomalies and to provide more transparency to the underlying dynamics in computer networks.

Committee:
     PRESIDENT: ROBERT, YVES
     SECRETARI: ARMEJACH SANOSA, ADRIÀ
     VOCAL: AGULLO, EMMANUEL
Thesis abstract: This work focuses on improving the efficiency of iterative methods for solving large and sparse linear systems.These problems arise in many fields, including climate modeling, molecular and fluid dynamics, among others.To solve them, iterative methods such as the Conjugate Gradient (CG) and Generalized Minimal Residual (GMRES) methods are widely employed.Their efficiency heavily depends on the choice of preconditioners, which accelerate convergence by improving the numerical properties of the system.Sparse Approximate Inverse (SAI) preconditioners, and their factorized variant (FSAI) for symmetric positive definite systems, are particularly appealing due to their parallel-friendly nature and straightforward application via Sparse Matrix-Vector (SpMV) operations.State-of-the-art SAI and FSAI approaches define their sparsity patterns primarily based on numerical considerations.This work introduces novel architecture-aware preconditioners designed to enhance performance by optimizing the sparse pattern selection process.The first contribution presents the Factorized Sparse Approximate Inverse with Pattern Extension (FSAIE) preconditioner, an optimized version of FSAI tailored for shared memory CPU architectures.FSAIE introduces a cache-aware algorithm that extends sparsity patterns, improving both the numerical effectiveness of FSAI and its computational efficiency.Additionally, a filtering-out strategy is proposed to remove numerically insignificant entries, reducing computational cost without compromising convergence.These techniques enhance data locality in the SpMV kernel by ensuring that extended sparse patterns align with cache-line-sized memory access patterns.The second contribution extends FSAIE to distributed memory CPU environments, introducing the Communication-aware Factorized Sparse Approximate Inverse with Pattern Extension (FSAIE-Comm) preconditioner.FSAIE-Comm incorporates communication-awareness to ensure that the sparse pattern extension does not introduce unnecessary inter-process communication overhead.To prevent load imbalance, an innovative strategy is developed to distribute computational workload more evenly.The third contribution focuses on GPU execution by introducing the GPU-aware Factorized Sparse Approximate Inverse (GFSAI) preconditioner.By structuring the sparse pattern to enhance coalesced memory accesses and exploit GPU-specific architectural characteristics, GFSAI significantly accelerates FSAI computations on GPUs.The final contribution generalizes the architecture-aware preconditioning strategies beyond FSAI by introducing the Communication-aware Sparse Approximate Inverse with Pattern Extension (SAIE-Comm) preconditioner.This approach optimizes SAI for distributed memory environments, similar to FSAIE-Comm, but is adapted for general linear systems where the GMRES solver is preferable over CG.SAIE-Comm highlights the versatility and flexibility of the proposed optimizations, demonstrating that architecture- and communication-aware pattern extensions can be effectively integrated into different preconditioning strategies and solver frameworks.By integrating hardware-aware considerations into preconditioner design, this research advances the state of the art in iterative solvers and contributes to the development of scalable and high-performance numerical methods.The proposed methods achieve substantial improvements in time-to-solution across diverse High-Performance Computing (HPC) architectures, with reductions ranging from 12.94% to 26.43% on five different CPU architectures—Intel Skylake, Power9, Zen 2, A64FX, and Intel Sapphire Rapids—and from 23.83% to 26.07% on two GPU architectures—Volta and Vega20—when applied to representative sparse matrix benchmarks.These results underscore the impact of architecture-aware preconditioning strategies in modern HPC applications, paving the way for more efficient and scalable iterative solvers.

Committee:
     PRESIDENT: BEAMER, SCOTT
     SECRETARI: MARTORELL BOFILL, XAVIER
     VOCAL: BOURGEAT, THOMAS EMILE
Thesis abstract: Modern computer systems have become universally heterogeneous. Computer architects have addressed the slowdown of Moore’s Law and the end of Dennard scaling by incorporating a variety of cores, including multi-core and many-core designs, and more recently, by integrating specialised hardware components both inside and outside the chip. While current commercial CPUs offer hundreds of cores in the server market, CPUs designed for laptops and mobile devices feature manycore architectures alongside a myriad of accelerators for tasks such as audio processing, video decoding, security, and machine learning (ML).The current era, often referred to as the golden age of computer architecture, has been driven by the design of accelerators aimed at achieving maximum performance. A significant enabler of this trend has been the open-source RISC-V instruction set architecture (ISA). By removing licensing costs, RISC-V has democratised hardware design and facilitated collaboration between industry and academia. This has led to a proliferation of proposals for new CPUs, GPUs, and accelerators, and RISC-V-based designs are beginning to see commercial adoption.However, this growing heterogeneity on the hardware side has substantially increased software complexity at all levels — from device drivers and operating systems to libraries and final applications. To optimise software effectively, engineers must now have a detailed understanding of the hardware platforms on which their code will execute. These platforms may integrate CPUs, GPUs, FPGAs, and domain-specific accelerators, making memory management, software compatibility, and data movement strategies significantly more complex. Although mature frameworks exist for GPU programming, especially in the context of ML, emerging accelerators still lack robust, general-purpose software solutions.Machine learning applications, in particular, have introduced unprecedented demands on computation, memory, storage, and networking. Companies such as Google, AWS, and Meta have responded by developing dedicated ML accelerators, advanced networking solutions, and even custom supercomputers to handle the scale and performance requirements. Moreover, petabyte-scale datasets have become commonplace not only in ML but also in big data analytics, genomics, and physics simulations. At this scale, efficient data movement is critical — not only across data centres but also within chips — to ensure fast and reliable communication among the components of heterogeneous systems.In this thesis, we characterise and develop new tools for researching heterogeneous systems, scaling and improving RTL simulations, enabling flexible on-chip communication between accelerators, and finally, proposing an innovative solution for data movement at the data centre level.

Committee:
     PRESIDENT: DE LA CRUZ MARTÍNEZ, RAÚL
     SECRETARI: AYGUADÉ PARRA, EDUARD
     VOCAL: KLINKENBERG, JANNIS
Thesis abstract: The growing complexity of contemporary multi-core and heterogeneous architectures necessitates parallel programming models capable of efficiently leveraging the available computational resources while ensuring performance, safety and programmability. OpenMP has emerged as the de facto standard for shared-memory parallel programming, offering a straightforward and adaptable approach to task-based execution. Nevertheless, despite its widespread adoption, OpenMP lacks support for key aspects such as memory locality in task scheduling on standard (non-NUMA) architectures and adaptability to runtime conditions in the scope of high-performance computing and fault tolerance for real-time systems, leading to suboptimal performance across various applications.As a consequence, this thesis presents a set of techniques aimed at addressing these limitations. The first contribution is an affinity-aware scheduling technique designed to improve data locality and cache utilization, thereby minimizing memory access overhead. The second contribution introduces a dynamic variant selection mechanism that adapts function execution to runtime conditions, enhancing adaptability and performance portability. The third contribution proposes a task replication mechanism to enhance fault tolerance, promoting system reliability in safety-critical applications. Lastly, we integrate OpenMP into a model-driven engineering framework to enable the automated generation of parallel code for cyber-physical systems, bridging the gap between high-performance and embedded systems.Through these advancements, this research elevates the OpenMP programming model by improving performance, safety, and programmability, making it more suitable for both high-performance computing and critical real-time embedded systems domains.

Committee:
     PRESIDENT: FELBER, PASCAL AMÉDÉE BERNARD
     SECRETARI: CANAL CORRETGER, RAMON
     VOCAL: NEMIROVSKY, MARIO DANIEL
Thesis abstract: Since we are reaching the boundaries of the trifecta of Von Neumann architectures, Moore’s Law and Dennard’s scaling, both software developers and hardware architects are forced to find better and novel approaches to exploit parallelism to improve the processing time of commodity and High Performance Computing (HPC) CPUs on the vast amount of data generated daily.As Von Neumann architectures, Moore’s Law, and Dennard’s scaling near their limits, new strategies are needed to improve the performance and efficiency of CPUs for data-intensive workloads. While ILP and TLP are widely explored, there is still untapped potential in Data-Level Parallelism (DLP), which vector architectures leverage via SIMD execution. These architectures perform well in workloads with regular memory access, such as dense linear algebra or image processing. However, many modern applications—including sparse linear algebra, databases, and genome analysis—exhibit irregular access patterns, leading to poor performance on commercial vector systems like AVX-512 and ARM SVE.Irregular workloads face three main challenges: (i) large memory footprints that cause frequent off-chip accesses and memory-bound behavior, (ii) underutilized memory bandwidth due to poor spatial locality, and (iii) low ILP and vector unit underutilization from fragmented access patterns. This thesis addresses these issues by introducing three vector acceleration frameworks tailored to these domains: VIA, VAQUERO, and QUETZAL.We begin with sparse linear algebra, where indirect accesses and sparsity hinder performance despite software optimizations like tiling. To address this, we propose VIA, a vector architecture with a tightly-coupled scratchpad memory that enhances locality and bandwidth utilization. VIA improves performance in key kernels (e.g., SpMV, SpMM) over leading libraries.Database workloads share irregularity but involve larger working sets and rely on different locality techniques. These patterns limit VIA’s effectiveness. We therefore propose VAQUERO, a vector accelerator with a scratchpad coherent with the CPU cache, enabling efficient processing of large-scale queries like joins and aggregations.In genome sequence analysis, long-read technologies demand high-throughput, low-latency processing. These workloads involve highly irregular and unaligned memory access, often with compacted data formats. To address this, we present QUETZAL, a vector architecture with hardware support for unaligned accesses and new vector instructions optimized for sequence alignment and edit distance computation.All three accelerators are implemented at RTL and synthesized for a 7nm node. VIA achieves a 5.5x speedup in sparse algebra, VAQUERO a 2.7x speedup in databases, and QUETZAL a 5.7x boost in genome analysis, all with only ~1% area overhead. Together, these designs show how targeted architectural innovation can close the performance gap for irregular workloads across key computational domains.

Committee:
     PRESIDENT: HERNANDEZ LUZ, CARLES
     SECRETARI: CANAL CORRETGER, RAMON
     VOCAL: GRAN TEJERO, RUBEN
Thesis abstract: The dissertation, research on enhancing timing predictability and performance for Critical Real-Time Embedded Systems (CRTES), focusing on Multi-Processor Systems on Chip (MPSoCs). CRTES are essential in critical domains like automotive and avionics, where complex functionalities and high performance are increasingly required for operations such as AI and multi-sensor data processing. However, MPSoCs face significant timing verification and validation (V&V) challenges, especially related to shared resources like caches and interconnects, which can introduce unpredictable delays. This thesis addresses three core areas to improve CRTES predictability: cache coherence, interconnection predictability, and application performance through vector extensions.Cache Coherence: In MPSoCs, cache coherence protocols ensure consistent data across multiple cores, but shared caches introduce contention that affects timing predictability. Traditional approaches to improving coherence often involve modifying protocols, a costly and complex task. This thesis takes an alternative approach by leveraging hardware event monitors (HEMs) to observe cache contention, providing valuable data for timing V&V without altering existing protocols. This methodology is applied to commercial MPSoCs like the NXP T1040 and T2080, which are widely used in real-time domains.On another note, the Remote Protocol-Contention Tracking (RPCT) method is proposed, which enables fine-grained tracking of delays due to inter-core contention, offering insights into cache coherence impacts on software predictability and informing developers on optimization strategies. Additionally, the thesis proposes a novel Multiple HEM Validation (MHV) method to improve the accuracy of contention measurements by validating HEM reliability through inter-HEM relationships, mitigating known issues with single-event HEM inaccuracies.Interconnections: MPSoCs rely on point-to-point (P2P) communication protocols like AXI4 for data transfer between cores, but the standard AXI protocol lacks timing constraints, making it unpredictable under real-time requirements. Addressing this, this thesis introduces AXI4 Real-Time (AXI4RT), an extension to the AXI protocol that specifies timing parameters to control the duration of transactions between manager and subordinate interfaces. By defining timing guarantees directly within the protocol, AXI4RT ensures predictable communication, enhancing system reliability for real-time applications. Additionally, this thesis provides some initial steps for contention tracking on modern AXI5 interconnects by doing an in-depth analysis how can contention be tracked with currently available HEMs and proposing some HEMs that could improve this tracking.Application Performance with Vector Extensions: To meet growing performance demands in CRTES, MPSoCs often use GPUs and custom accelerators, but these present certification challenges due to their complexity and unpredictable timing. This thesis explores using vector extensions (VExt) as an alternative. Single Instruction Multiple Data (SIMD) processing units are already available in many embedded processors, which perform parallel operations on multiple data elements, effectively improving data processing speeds. Unlike GPUs, VExt are integrated within processors and comply with high-integrity system standards, making them easier to certify. The thesis provides an analysis of VExt in COTS processors like NVIDIA’s AGX Xavier and show their potential to enhance performance while maintaining compliance with standards such as MISRA-C.In summary, this thesis advances the state-of-the-art in CRTES predictability, presenting solutions that ensure more reliable timing for complex embedded systems in safety-critical applications. By addressing cache coherence, interconnect timing, and performance, this thesis provides tools and methodologies for better timing analysis, enabling MPSoCs to improve real-time guarantees.

Committee:
     PRESIDENT: RECH, PAOLO
     SECRETARI: PEÑA MONFERRER, ANTONIO JOSE
     VOCAL: LENTARIS, GEORGE
Thesis abstract: This thesis titled “Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments" explores the challenges and solutions for integrating high-performance Commercial Off-The-Shelf (COTS) System-on-Chip (SoC) technologies, specifically GPUs, into space applications. These automotive-grade systems offer significant computational capabilities but face unique challenges in radiation-intense environments typical of space. The research investigates these challenges and proposes solutions to enhance the reliability of such systems. A key component of the thesis involves the comprehensive evaluation of modern embedded GPUs under space-like conditions, including exposure to proton and heavy-ion radiation. This analysis identifies vulnerabilities such as Single Event Effects (SEE) , which can cause faults like Single Event Upset (SEU), Single Event Functional Interrupt (SEFI), and Single Event Latch-up (SEL). To support these evaluations, the author develops the OBPMark suite, an open-source benchmark tailored for assessing the performance and efficiency of GPUs in space-specific computational tasks. To address the faults identified, the thesis proposes innovative software-based fault mitigation strategies. These include the design of fault-tolerant GPU kernels and middleware solutions that improve error detection and recovery. The effectiveness of these methods is demonstrated through both simulation and radiation testing. Additionally, the research presents hardware-level innovations, such as the development of application-specific integrated circuits (ASICs) and specialized printed circuit boards (PCBs), to enhance system resilience without compromising performance. This work significantly contributes to the field of space computing by creating a robust framework for evaluating and mitigating radiation effects in complex COTS SoCs. It bridges the gap between the cost-effectiveness and performance of commercial technologies and the reliability demands of space-grade applications. The findings of this thesis pave the way for the adoption of high-performance embedded GPUs in future space missions.

Committee:
     PRESIDENT: PEDERSEN, JENS MYRUP
     SECRETARI: SOLE PARETA, JOSEP
     VOCAL: CALLEGATI, FRANCO
Thesis abstract: This thesis explores how to enhance the performance of cloud applications by addressing inefficiencies across both the network and compute layers of modern distributed systems. As cloud-native applications grow more complex and are deployed across heterogeneous, geographically distributed infrastructures, traditional abstractions, though foundational for scalability and modularity, have begun to constrain opportunities for global coordination and responsiveness. To overcome these limitations, this work introduces two complementary approaches: one that improves network resource utilization without requiring developer involvement, and another that enhances compute-side elasticity through a smarter, more proactive autoscaling mechanism. Both approaches are guided by a common design philosophy: introducing context-aware intelligence in a minimally disruptive way, maintaining full compatibility with existing architectures, infrastructure, and developer workflows.The first part of the thesis focuses on Network-Application Integration (NAI), specifically targeting performance improvements in inter-datacenter communication. To this end, it proposes an application-agnostic solution based on extended Berkeley Packet Filter (eBPF) and eXpress Data Path (XDP) technologies. By dynamically identifying and separating short and long Transmission Control Protocol (TCP) flows at the network ingress, the system enables differentiated routing through distinct network tunnels, thereby mitigating queuing delays and reducing flow completion times. A key advantage of this approach is that it operates transparently, requiring no modifications to applications or developer-provided annotations, making it highly deployable within existing environments. Testbed experiments demonstrate that this technique significantly reduces latency and improves resource utilization in hybrid, multi-datacenter scenarios.The second part of the thesis turns to the compute domain, focusing on autoscaling mechanisms in Kubernetes-managed microservice environments. Recognizing the limitations of existing reactive scaling strategies, the work develops a control-theoretic model of the Kubernetes Horizontal Pod Autoscaler (HPA), formally analyzing its stability and responsiveness. Based on these insights, a new context-aware HPA is introduced, which incorporates upstream CPU metrics from the application’s service graph to anticipate downstream load changes. This proactive strategy enables more efficient and stable scaling decisions, improving responsiveness and reducing latency during traffic spikes. Notably, it achieves these gains without relying on complex performance models or machine learning, preserving simplicity and compatibility with standard Kubernetes tooling.Overall, the two approaches presented in this thesis offer practical methods for improving the performance and efficiency of distributed cloud applications, with a focus on compatibility with existing systems and workflows. Rather than proposing disruptive architectural changes, both solutions extend current abstractions to introduce additional context-awareness where it can be most effective. The results suggest that incremental, deployable enhancements to orchestration and networking layers can help address emerging challenges in scalability and responsiveness, making them suitable candidates for integration into real-world cloud-native environments.

Committee:
     PRESIDENT: DURAN BARROSO, RAMON J.
     SECRETARI: MARIN TORDERA, EVA
     VOCAL: KOURTIS, MICHAIL ALEXANDROS
Thesis abstract: This thesis presents a Federated Learning-based Smart Advertising System designed to enhance user engagement, optimize network efficiency, and ensure data privacy in digital advertising. Traditional advertising systems face significant challenges in balancing personalization with privacy, managing network overhead, and scaling efficiently. This study addresses these issues by integrating Edge Computing and Federated Learning (FL) to enable real-time, decentralized ad targeting while keeping user data secure.The proposed system consists of a decentralized recommendation engine, where local models are trained on users’ devices and aggregated using meta-heuristic optimization techniques, particularly the Whale Optimization Algorithm (WOA). Experimental results demonstrate that WOA outperforms other aggregation techniques, such as the Firefly Algorithm (FA) and Bat Algorithm (BA), in terms of convergence speed and overall efficiency. The system also leverages formal verification techniques, including model checking, to ensure correctness, security, and compliance with privacy regulations.Comprehensive evaluation through both simulated and real-world case studies (such as the AROUND system) shows that the proposed architecture reduces network traffic, minimizes computational overhead, and significantly improves Click-Through Rates (CTR) and user engagement compared to traditional centralized models. The system is particularly beneficial for applications in museums, shopping malls, and retail chains, providing real-time tracking, indoor mapping, and personalized content delivery.The findings underscore the potential of Federated Learning and Edge Computing in privacy-preserving smart advertising, offering a scalable, cost-efficient, and user-centric solution for the future of digital marketing.