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Doctoral candidates who complete a doctoral degree will have acquired the following competencies, which are needed to carry out quality research (Royal Decree 99/2011, of 28 January, which regulates official doctoral studies):

a) A systematic understanding of the field of study and a mastery of the research skills and methods related to the field.
b) An ability to conceive, design or create, put into practice and adopt a substantial process of research or creation.
c) An ability to contribute to pushing back the frontiers of knowledge through original research.
d) A capacity for critical analysis and an ability to assess and summarise new and complex ideas.
e) An ability to communicate with the academic and scientific community and with society in general as regards their fields of knowledge in the manner and languages that are typical of the international scientific community to which they belong.
f) An ability to foster scientific, technological, social, artistic and cultural progress in academic and professional contexts within a knowledge-based society.

The award of a doctoral degree must equip the graduate for work in a variety of settings, especially those requiring creativity and innovation. Doctoral graduates must have at least acquired the personal skills needed to:

a) Develop in contexts in which there is little specific information.
b) Find the key questions that must be answered to solve a complex problem.
c) Design, create, develop and undertake original, innovative projects in their field.
d) Work as part of a team and independently in an international or multidisciplinary context.
e) Integrate knowledge, deal with complexity and make judgements with limited information.
f) Offer criticism on and intellectually defend solutions.

Finally, with respect to competencies, doctoral students must:

a) have acquired advanced knowledge at the frontier of their discipline and demonstrated, in the context of internationally recognised scientific research, a deep, detailed and well-grounded understanding of theoretical and practical issues and scientific methodology in one or more research fields;
b) have made an original and significant contribution to scientific research in their field of expertise that has been recognised as such by the international scientific community;
c) have demonstrated that they are capable of designing a research project that serves as a framework for carrying out a critical analysis and assessment of imprecise situations, in which they are able to apply their contributions, expertise and working method to synthesise new and complex ideas that yield a deeper knowledge of the research context in which they work;
d) have developed sufficient autonomy to set up, manage and lead innovative research teams and projects and scientific collaborations (both national and international) within their subject area, in multidisciplinary contexts and, where appropriate, with a substantial element of knowledge transfer;
e) have demonstrated that they are able to carry out their research activity in a socially responsible manner and with scientific integrity;
f) have demonstrated that they are able to participate in scientific discussions at the international level in their field of expertise and disseminate the results of their research activity to audiences of all kinds;
g) have demonstrated, within their specific scientific context, that they are able to make cultural, social or technological advances and promote innovation in all areas within a knowledge-based society.

Number of places

40

Duration of studies and dedication regime

Duration
The maximum period of study for full-time doctoral studies is three years, counted from the date of admission to the programme to the date of submission of the doctoral thesis. The academic committee of the doctoral programme may authorise a doctoral candidate to pursue doctoral studies on a part-time basis. In this case, the maximum period of study is five years, counting from the date of admission to the programme to the date of submission of the doctoral thesis. For calculating these periods, the date of admission is considered to be the date of the first enrolment for tutorials, and the date of submission the moment in which the Doctoral School officially deposits the doctoral thesis.

For full-time doctoral candidates, the minimum period of study is two years, counted from the date of an applicant's admission to the programme until the date on which the doctoral thesis is deposited; for part-time doctoral candidates it is four years. When there are justified grounds for doing so, and the thesis supervisor and academic tutor have given their authorisation, doctoral candidates may request that the academic committee of their doctoral programme exempt them from the minimum period of study requirement.

The calculation of periods of study will not include periods of absence due to illness, pregnancy or any other reason provided for in the regulations in force. Students who find themselves in any of these circumstances must notify the academic committee of the doctoral programme, which, where appropriate, must inform the Doctoral School. Doctoral candidates may also temporarily withdraw from the programme for up to one year, and this period may be extended for an additional year. Doctoral candidates who wish to interrupt their studies must submit a justified request to the academic committee of the doctoral programme, which will decide whether or not to approve the request. Each programme will establish conditions for readmission to doctoral studies.

Extension
If full-time doctoral candidates have not applied to deposit their thesis by the end of the three-year period of study, the academic committee of the programme may authorise an extension of up to one year. In exceptional circumstances, a further one-year extension may be granted, subject to the conditions established by the corresponding doctoral programme. In the case of part-time doctoral candidates, an extension of two years may be authorised. In both cases, in exceptional circumstances a further one-year extension may be granted by the Doctoral School's Standing Committee, upon the submission of a reasoned application by the academic committee of the doctoral programme.

Dismissal from the doctoral programme
A doctoral candidate may be dismissed from a doctoral programme for the following reasons:

• The doctoral candidate submitting a justified application to withdraw from the programme.
• The maximum period of study and of extensions thereof ending.
• The doctoral candidate not having enrolled every academic year (unless he or she has been authorised to temporarily withdraw).
• The doctoral candidate failing two consecutive assessments.
• The doctoral candidate having disciplinary proceedings filed against him or her that rule that he or she must be dismissed from the UPC.

Dismissal from the programme implies that doctoral candidates cannot continue studying at the UPC and the closing of their academic record. This notwithstanding, they may apply to the academic committee of the programme for readmission and the committee must reevaluate them in accordance with the criteria established in the regulations.

Organization

• Careglio, Davide

• Ayguade Parra, Eduard
• Barcelo Ordinas, Jose Maria
• Careglio, Davide

• Department of Computer Architecture (PROMOTORA)

Doctoral Unit - ICT North Campus Management and Support Unit (UTGCNTIC). C. Jordi Girona, 1-3. Building B4-003 (North Campus)
Tel.: 934 054 198
E-mail: doctorat.ac@upc.edu

Agreements with other institutions

BSC (Barcelona Supercomputing Center)

Access profile

Access requirements

Applicants must hold a Spanish bachelor’s degree or equivalent and a Spanish master’s degree or equivalent, provided they have completed a minimum of 300 ECTS credits on the two degrees (Royal Decree 43/2015, of 2 February)

In addition, the following may apply:

• Holders of an official degree awarded by a university in Spain or any other country in the European Higher Education Area, pursuant to the provisions of Article 16 of Royal Decree 1393/2007, of 29 October, which establishes official university course regulations, who have completed a minimum of 300 ECTS credits on official university degrees, of which at least 60 must be at the master's degree level.
• Holders of an official Spanish bachelor’s degree comprising at least 300 credits, as provided for by EU regulations. Holder of degrees of this kind must complete bridging courses unless the curriculum of the bachelor’s degree in question included research training credits equivalent in value to those which would be earned on a master's degree.
• Holders of an official university qualification who, having passed the entrance examination for specialised medical training, have completed at least two years of a training course leading to an official degree in a health-sciences specialisation.
• Holders of a degree issued under a foreign education system. In these cases, homologation is not required, but the UPC must verify that the degree certifies a level of training equivalent to an official Spanish master's degree and qualifies the holder for admission to doctoral studies in the country where it was issued. Admission on this basis does not imply homologation of the foreign degree or its recognition for any purpose other than admission to doctoral studies.
• Holders of a Spanish doctoral qualification issued under previous university regulations.

Note 1: Doctoral studies entrance regulations for holders of an undergraduate degree awarded before the introduction of the EHEA (CG 47/02 2014)

Note 2: Governing Council Decision 64/2014, which approves the procedure and criteria for assessing the fulfilment of academic admission requirements for doctoral studies by holders of non-homologated foreign degrees (CG 25/03 2014)

Admission criteria and merits assessment

Given the highly heterogeneous academic environment, to ensure that applicants have an appropriate background, the programme has modified its internal admission procedure. Admission requirements are now grouped in two categories: formal and conceptual. If an applicant does not meet the formal conditions, the conceptual requirements are not considered.

Formal analysis (FA)

Applicants must meet the requirements established in the administrative regulations for programme. The focus here is on ensuring that applicants have the level of studies and the number of credits required. Applicants who do not meet these requirements will not be admitted to the programme.

Conceptual analysis (CA)

This includes points related to the applicant’s level of knowledge and capabilities. Another factor taken into account is whether there is a research group interested in the work the applicant wishes to undertake. In this section, the following requirements apply:

• ED: An engineering degree related to the subject area of the programme, preferably in informatics or telecommunications. In exceptional cases, students with other qualifications, such as a degree in mathematics or a master's degree in computer science, may also be admitted.

• RG: Whether or not the applicant has the support of a research group linked to the programme and a supervisor/tutor to complete their doctoral thesis.

• BA: Experience or explicit knowledge of computer architecture; acquired, for example, by completing a master’s thesis in this area, collaborating with a group working in the field, etc.

• EN: Proficiency in English, certified by an internationally accepted testing system (TOEFL, etc.).

• FU: Availability of funding for the student’s research, whether through the institution where they completed their previous studies or through the group in which the thesis work would be carried out.

All of these factors will be taken into account by applying the following formula:
Admission: FA*(0.1ED + 0.4RG + 0.1BA + 0.2EN + 0.2FU)

Training complements

To ensure that students admitted to the programme have the knowledge they need to make good progress, the academic committee of the doctoral programme may require that they pass specific bridging courses. Additional training requirements will be determined based on each student's academic background. In such cases, the committee will keep track of the bridging courses completed and establish appropriate criteria to limit their duration. Bridging courses may provide research or cross-disciplinary training, but in no case may doctoral students be required to enrol for 60 or more ECTS credits. Taking into account the doctoral student activity report, the academic committee may propose measures that complement those specified in the regulations and which result in doctoral students who do not meet the specified requirements being excluded from the programme.

Therefore, the organisers of the doctoral programme may admit students on the condition that they complete specific bridging courses to fill gaps identified in their academic background and ensure that they have the knowledge needed to successfully complete their doctoral studies. The number of bridging courses required will depend on each student's background and may require the completion of 18 or 30 additional ECTS credits. The following considerations will apply: 

• Credits for additional training will correspond to three or five master's level subjects, selected from among master’s degrees linked to the doctoral programme. 

• The academic committee will decide how many credits a student must take by reviewing the subjects they took to earn their entrance qualification in order to identify possible gaps in their knowledge. A range of factors are taken into account to determine what subjects a student must take. Apart from subject names, other points considered include the number of hours of study completed for each subject, the topics covered, and even the university where the subjects were taken. The syllabus for each subject will be reviewed, with particular attention to the number of hours allocated in the syllabus. 

• The specific subjects to be taken will be determined by the academic committee in agreement with the student's tutor. Subjects will be selected with the aim of achieving two key goals: i) increasing the student’s knowledge in areas where gaps have been identified; ii) increasing their knowledge in the area of their doctoral thesis.

Enrolment period for new doctoral students

Students enrolling in the doctoral programme for the first time must do so by the deadline specified in the admission decision.
Unless otherwise expressly indicated, enrolments corresponding to admission decisions issued from the second half of April on must be completed within the ordinary enrolment period for the current academic year. 

More information at the registration section for new doctoral students

Enrolment period

Ordinary period for second and successive enrolments: first half of October.

More information at the general registration section

Procedure for the preparation and defense of the research plan

Doctoral candidates must submit a research plan, which will be included in their doctoral student activity report, before the end of the first year. The plan may be improved over the course of the doctoral degree. It must be endorsed by the tutor and the supervisor, and it must include the method that is to be followed and the aims of the research.

At least one of these annual assessments will include a public presentation and defence of the research plan and work done before a committee composed of three doctoral degree holders, which will be conducted in the manner determined by each academic committee. The examination committee awards a Pass or Fail mark. A Pass mark is a prerequisite for continuing on the doctoral programme. Doctoral candidates awarded a Fail mark must submit a new research plan for assessment by the academic committee of the doctoral programme within six months.

The committee assesses the research plan every year, in addition to all of the other activities in the doctoral student activity report. Doctoral candidates who are awarded two consecutive Fail marks for the research plan will be obliged to definitely withdraw from the programme.

If they change the subject of their thesis, they must submit a new research plan.

Formation activities

Tutorial hours are considered highly important for training students and monitoring their progress. Time spent on tutorials is estimated as follows:

Activity: Tutorial.

Hours: 2 hours/week × 48 weeks of class × 3 years = 288 hours. 

Type: compulsory

In weekly tutorials, students will discuss their work and the progress they are making with their tutor. Tutors may provide students with guidance based on the results obtained and anticipated progress with the aim of facilitating achievement of objectives that have been set. During the hours allocated for these sessions, tutors may also talk to students about research groups that are working in areas closely related to the topic of their thesis and that may be interested in engaging with the work to be carried out by the student, or that it may be worthwhile for the student to contact to discuss possible collaborations. Tutorials may also include internal meetings with other members of the research group to discuss issues of common interest in relation to the research being conducted.

This activity will continue throughout the time that it takes a student to complete their doctoral thesis (estimated at three years).

Procedure for assignment of tutor and thesis director

The academic committee of the doctoral programme assigns a thesis supervisor to each doctoral candidate when they are admitted or enrol for the first time, taking account of the thesis supervision commitment referred to in the admission decision.

The thesis supervisor will ensure that training activities carried out by the doctoral candidate are coherent and suitable, and that the topic of the candidate’s doctoral thesis will have an impact and make a novel contribution to knowledge in the relevant field. The thesis supervisor will also guide the doctoral candidate in planning the thesis and, if necessary, tailoring it to any other projects or activities undertaken. The thesis supervisor will generally be a UPC professor or researcher who holds a doctoral degree and has documented research experience. This includes PhD-holding staff at associated schools (as determined by the Governing Council) and UPC-affiliated research institutes (in accordance with corresponding collaboration and affiliation agreements). When thesis supervisors are UPC staff members, they also act as the doctoral candidate’s tutor.

PhD holders who do not meet these criteria (as a result of their contractual relationship or the nature of the institution to which they are attached) must be approved by the UPC Doctoral School's Standing Committee in order to participate in a doctoral programme as researchers with documented research experience.

The academic committee of the doctoral programme may approve the appointment of a PhD-holding expert who is not a UPC staff member as a candidate’s thesis supervisor. In such cases, the prior authorisation of the UPC Doctoral School's Standing Committee is required. A UPC staff member who holds a doctoral degree and has documented research experience must also be proposed to act as a co-supervisor, or as the doctoral candidate’s tutor if one has not been assigned.

A thesis supervisor may step down from this role if there are justified reasons (recognised as valid by the committee) for doing so. If this occurs, the academic committee of the doctoral programme will assign the doctoral candidate a new thesis supervisor.

Provided there are justified reasons for doing so, and after hearing any relevant input from the doctoral candidate, the academic committee of the doctoral programme may assign a new thesis supervisor at any time during the period of doctoral study.

If there are academic reasons for doing so (an interdisciplinary topic, joint or international programmes, etc.) and the academic committee of the programme gives its approval, an additional thesis supervisor may be assigned. Supervisors and co-supervisors have the same responsibilities and academic recognition.

The maximum number of supervisors of a doctoral thesis is two: a supervisor and a co-supervisor.

For theses carried out under a cotutelle agreement or as part of an Industrial Doctorate, if necessary and if the agreement foresees it this maximum number of supervisors may not apply. This notwithstanding, the maximum number of supervisors belonging to the UPC is two.

More information at the PhD theses section

Permanence

The academic committee of the programme may authorise an extension of up to one year for full-time doctoral candidates who have not applied to deposit their thesis by the end of the three-year period of study, in the terms outlined in the Academic Regulations for Doctoral Studies of the Universitat Politècnica de Catalunya. In the case of part-time candidates, an extension of two years may be authorised. In both cases, in exceptional circumstances a further one-year extension may be granted by the Doctoral School's Standing Committee, upon the submission of a reasoned application by the academic committee of the doctoral programme.

A doctoral candidate may be dismissed from a doctoral programme for the following reasons:

• The doctoral candidate submitting a justified application to withdraw from the programme.
• The maximum period of study and of extensions thereof ending.
• The doctoral candidate not having enrolled every academic year (unless he or she has been authorised to temporarily withdraw).
• The doctoral candidate failing two consecutive assessments.
• The doctoral candidate having disciplinary proceedings filed against him or her that rule that he or she must be dismissed from the UPC.

Dismissal from the programme implies that doctoral candidates cannot continue studying at the UPC and the closing of their academic record. This notwithstanding, they may apply to the academic committee of the programme for readmission and the committee must reevaluate them in accordance with the criteria established in the regulations.

International Mention

The doctoral degree certificate may include International Doctorate mention. In this case, the doctoral candidate must meet the following requirements:

a) During the period of study leading to the award of the doctoral degree, the doctoral candidate must have spent at least three months at a respected higher education institution or research centre outside Spain to complete courses or do research work. The stays and activities carried out must be endorsed by the thesis supervisor and authorised by the academic committee of the programme. The candidate must provide a certifying document issued by the person responsible for the research group of the body or bodies where the stay or activity was completed. This information will be added to the doctoral student’s activity report.
b) Part of the thesis (at least the summary and conclusions) must be written and presented in one of the languages commonly used for science communication in the relevant field of knowledge, which must not be an official language of Spain. This rule does not apply to stays and reports in Spanish or to experts from Spanish-speaking countries.
c) At least two PhD-holding experts belonging to a higher education institution or research centre outside Spain must have issued officially certified reports on the thesis.
d) The thesis examination committee must have included at least one PhD-holding expert from a higher education or research institution outside Spain who was not responsible for the candidate’s stay abroad (point a) above).
e) The thesis defence must have taken place on UPC premises or, in the case of joint programmes, at the location specified in the collaboration agreement.

List of authorized thesis for defense

• OSORIO RÍOS, JOHN HAIBER: Adapting floating-point precision to accelerate deep neural network training
  
  Author: OSORIO RÍOS, JOHN HAIBER
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Deposit date: 24/07/2023
  Reading date: 18/10/2023
  Reading time: 10:00
  Reading place: Sala E101 - Edifici C6 - FIB
  Thesis director: CASAS GUIX, MARC | ARMEJACH SANOSA, ADRIÀ
  Committee:
       PRESIDENT: DEFOUR, DAVID
       SECRETARI: MARTORELL BOFILL, XAVIER
       VOCAL: DE OLIVEIRA CASTRO HERRERO, PABLO
  Thesis abstract: Deep Neural Networks (DNNs) have become ubiquitous in a wide range of application domains. Despite their success, training DNNs is an expensive task which has motivated the use of reduced numerical precision formats to improve performance and reduce power consumption. Emulation techniques are a good fit for understanding the properties of new numerical formats on a particular workload. However, current state-of-the-art techniques cannot perform these tasks quickly and accurately on a wide variety of workloads.The usage of Mixed Precision (MP) arithmetic with floating-point 32-bit (FP32) and 16-bit half-precision aims at improving memory and floating-point operations throughput, allowing faster training of bigger models. This is one of the most used techniques, and has been successfully applied to train DNNs. Despite its advantages in terms of reducing the need for key resources like memory bandwidth or register file size, it has a limited capacity for diminishing further computing costs, as it requires 32-bits to represent its output. On the other hand, full half-precision arithmetic fails to deliver state-of-the-art training accuracy.Several hardware companies are proposing native Brain Float 16-bit (BF16) support for neural network training. Fused Multiply- Add (FMA) functional units constitute a fundamental hardware component to train DNNs. Its silicon area grows quadratically with the mantissa bit count of the computer number format, which has motivated the adoption of the BF16. BF16 features 1 sign, 8 exponent and 7 explicit mantissa bits. Some approaches to train DNNs achieve significant performance benefits by using the BF16 format. However, these approaches must combine BF16 with the standard IEEE 754 FP32 format to achieve state-of-the-art training accuracy, which limits the impact of adopting BF16.To address all of the previous concerns with respect to different numerical formats, specific training techniques, and how to increase the use of reduced precision approaches, this Thesis proposes FASE, a Fast, Accurate, and Seamless Emulator that leverages dynamic binary translation to enable emulation of custom numerical formats. FASE is fast; allowing emulation of large unmodified workloads, accurate; emulating at instruction operand level, and seamless; as it does not require any code modifications and works on any application or DNN framework without any language, compiler or source code access restrictions. We evaluate FASE using a wide variety of DNN frameworks and large-scale workloads. Our evaluation demonstrates that FASE achieves better accuracy than coarser-grain state-of-the-art approaches, and shows that it is able to evaluate the fidelity of multiple numerical formats and extract conclusions on their applicability.To show the advantages of FASE we test it in object classification, natural language processing and generative networks workloads. We use FASE to analyze BF16 usage in the training phase of a 3D Generative Adversarial Network (3DGAN) simulating High Energy Physics detectors.We use FASE to characterize and analyze computer arithmetic to propose a seamless approach to dynamically adapt floating point arithmetic. Our dynamically adaptive methodology enables the use of full half-precision arithmetic for up to 96.4% of the computations when training state-of-the-art neural networks; while delivering comparable accuracy to 32-bit floating point arithmetic.Finally, we propose an approach able to train complex DNNs entirely using the BF16 format. Using FASE we introduce a new class of FMA operators, FMABF16_nm, that entirely rely on BF16 FMA hardware instructions and deliver the same accuracy as FP32. FMABF16_nm operators achieve performance improvements within the 1.28x-1.35x range on ResNet101 with respect to FP32. FMABF16_nm enables training complex DNNs on simple low-end hardware devices without requiring expensive FP32 FMA functional units.
  
• VIEIRA ZACARIAS, FELIPPE: Job scheduling for disaggregated memory in high performance computing systems
  
  Author: VIEIRA ZACARIAS, FELIPPE
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Deposit date: 20/07/2023
  Reading date: 09/10/2023
  Reading time: 14:00
  Reading place: Sala E101 - Edifici C6 de la Facultat d'Informàtica de Barcelona
  Thesis director: CARPENTER, PAUL MATTHEW | PETRUCCI, VINICIUS
  Committee:
       PRESIDENT: PINTO, CHRISTIAN
       SECRETARI: CORBALAN GONZALEZ, JULITA
       VOCAL: DOUDALI, THALEIA DIMITRA
  Thesis abstract: In a typical HPC cluster system, a node is the elemental component unit of this architecture. Memory and compute resources are tightly coupled in each node and the rigid boundaries between nodes limits compute and memory resource utilization. The problem is increased by the fact that HPC applications have a widely varying per-node memory footprint due to diverse application characteristics, differing problem sizes, and strong scaling. In fact, 25% to 76% of the system's total memory capacity typically remains idle. Disaggregated memory offers a way to improve memory utilization, as memory becomes a pool that can be dynamically composed to match the needs of the workloads. It enables fine-grained allocation of memory capacity to jobs while maintaining the cost-effectiveness and scalability of a cluster architecture. A key component for the distribution of computing power within the cluster infrastructure is the RJMS or simply resource manager. Its goal is to satisfy users' demands and achieve acceptable performance in the overall system utilization by efficiently matching requests to resources. Even though several researches on RJMS have been carried out to solve problems related to the current state-of-the-art on HPC systems, memory disaggregation is still under development. Therefore, adopting a disaggregated architecture means redesigning the resource manager services. In this thesis we propose an efficient memory disaggregated infrastructure for a cluster resource manager and its evaluation at scale through a structured simulated experimental methodology employing a contention model that models the impact of shared resources in disaggregated scenarios. Sharing common memory devices or interfaces in a disaggregated infrastructure may incur an unsatisfactory loss of performance because concurrent memory access can saturate the resource; we start our study by introducing a systematic methodology to build a contention model. Extensive real-machine experimentation and the results of workloads have shown that our contention model predicts performance degradation with at most an average error of 1.19% and max error of 14.6%. Compared with the state-of-the-art, the relative improvements are almost 24 % on average and 33% for the worst case. In sequence, we argue that it is possible to increase throughput and utilization using memory disaggregated in a resource manager. We show that depending on the level of imbalance between the system and memory demands of scheduled jobs, memory disaggregation enables resource savings of up to 33% compared to the state-of-the-art resource manager. In addition, on average, it can increase the memory utilization by a factor of 1.6, while having almost 90% of CPU utilization. In our study, we also investigate how critical memory demand bounds are for maximising system throughput and minimising job response time. We analyse to what degree the users would have a natural incentive to provide accurate memory bounds. We demonstrate that even when there is a large effect on system throughput (-25%) and response time (5 times higher), there is a very little direct incentive for the users to be accurate in their estimates, with only an 8% increase in response time. We further demonstrate that taking advantage of memory temporal and spatial imbalance among jobs delivers improvements up to 18% in throughput, 38% in throughput per dollar, and up to 69% reduction in job response time (median) when there are imbalanced memory usage and overestimated demands on underprovisioned systems. Overall, we believe our study provides valuable insights on the importance of design space exploration for disaggregated memory HPC systems. We demonstrate that by understanding disruptive architectural changes on future systems and the demands of the workloads, system provisioning can be carefully designed to achieve the best cost-benefit.
  

Last update: 04/10/2023 04:45:29.

List of lodged theses

• EL SAYED, AHMAD MOHAMMAD: Smart and efficient sensor network operation for 5G and beyond ecosystems
  
  Author: EL SAYED, AHMAD MOHAMMAD
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Deposit date: 28/09/2023
  Reading date: pending
  Reading time: pending
  Reading place: pending
  Thesis director: RUIZ RAMÍREZ, MARC | HARB, HASSAN
  Committee:
       PRESIDENT: SIDDIQUI, MUHAMMAD SHUAIB
       SECRETARI: BERRAL GARCÍA, JOSEP LLUÍS
       VOCAL: TABATABAEIMEHR, FATEMEHSADAT
  Thesis abstract: Sensor Networks (SN) will play an integral role in Beyond 5G (B5G) ecosystems, especially for highly-distributed use cases and services such as Digital Twins (DT). Thus, the underlying transport network needs to provide connectivity between the highly dense and distributed SNs and the DT manager, that typically runs far from sensor data sources, i.e., in a centralized server. In view of this, critical requirements such as high data throughput, latency sensitivity communication, and data veracity and integrity assurance are essential to be provided by B5G networks to support DT services. In order to meet such requirements, statistical and Artificial Intelligence (AI)-based SN data collection and analysis can be implemented to provide smart and efficient data transmission. By means of those procedures, SN data can be compressed and analyzed locally in order to reduce the total data volume to be conveyed in the centralized server. In addition, the inherent nature of the compression and analysis algorithms add privacy and security to the transmitted data without affecting integrity. The use of these kind of AI-based techniques opens the opportunity to perform Knowledge Transfer (KT) between DTs operating under the same tenant infrastructures. Since sharing raw data poses a privacy breach, AI-based methods allow interchanging relevant information while obfuscating critical details, thus enabling coordinated operation across differentiated segments.This Ph.D. thesis aims at enhancing the operation of dense SNs, which are supported by an underlying transport infrastructure that includes edge/fog computing capabilities distributed among nodes. Through the application of statistical and AI-based methods and procedures, the proposed methods will target several objectives, such as reducing the volume of data transported through the network while keeping privacy and integrity, detecting anomalies or events in the collected data to provide early alarms and notifications, and facilitating the operation of services across several SN domains.In more detail, the first objective is to develop methods to reduce the volume of collected sensor data through statistical and AI-based methods for data compression and sampling rate manipulation. We proposed both statistical-based and Autoencoder (AE)-based approaches for compression, as wells as sampling rate adaptation method that works with either. Simulations of implemented algorithms on real world datasets showed a significant ability to reduce the volume of the data, reaching 1% of its original size in some cases, and leading the reduced energy consumption in the factor of one-tenth in case of sensors with limited energy availability.The second objective is to develop methods for maintaining data veracity through employing AI-based anomaly detection methods at multiple levels of the network. Anomalies may arise due to a range of factors from faulty sensors to malicious attacks and detecting them can facilitate timely actions to avoid or mitigate their effect. We proposed two AE-based methods: one operating at the sensor level, and the other on the network level. Simulations of implemented algorithms on real world datasets showed more than 90% of accuracy in detecting anomalies in single sensor data analysis. Moreover, prompt detection of subtle anomalies spanning multiple sensors that could not be detected by single sensor data analysis was achieved.Finally, the third objective is to investigate methods to improve multi-domain DT systems management and coordination through KT while preserving the privacy of each individual DT. We proposed an AE-based knowledge extraction method that extracts codified information about the state of the sharing DT and sends it to the target DT. The method showed that the target DT is able to use the codified and private information about the state of the sharing DT before the changes are apparent through their effect on its system.
  
• REGGIANI, ENRICO: Efficient hardware acceleration of deep neural networks via arithmetic complexity reduction
  
  Author: REGGIANI, ENRICO
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Deposit date: 20/09/2023
  Reading date: pending
  Reading time: pending
  Reading place: pending
  Thesis director: CRISTAL KESTELMAN, ADRIAN | OLIVIERI, MAURO
  Committee:
       PRESIDENT: FELBER, PASCAL
       SECRETARI: CANAL CORRETGER, RAMON
       VOCAL: YALCIN, GULAY
  Thesis abstract: Over the past decade, significant progresses in the field of artificial intelligence have led to remarkable advancements in a widerange of technologies. Deep learning, a subfield of machine learning centered around deep neural networks (DNNs), has playeda pivotal role in driving these achievements. Indeed, DNNs have demonstrated unprecedented accuracy levels in tasks such asimage recognition, speech recognition, and natural language processing (NLP). However, the high computational demandassociated with current DNN models limits their applicability across different platforms and applications.Specifically, the constant increase in the number of parameters and operations required for DNN computations, and the growingcomplexity of their topologies and layers are posing obstacles for a wide range of computing systems, ranging from smallgeneral-purpose CPUs to hardware accelerators targeting HPC and cloud computing environments.In this thesis, we explore various research directions aimed at optimizing DNN computations on modern hardware architectures.We first investigate a novel mathematical technique, called binary segmentation, studiyng its applicability to reduce the arithmeticcomplexity of linear algebra operations involving narrow integers on general-purpose CPU architectures. Additionally, wepropose a novel hardware microarchitecture called Bison-e accelerating linear algebra kernels using binary segmentation. Wedemonstrate that Bison-e achieves up to 5.6×, 13.9×, and 24× improvement than a single RISC-V core in the computation ofconvolution and fully-connected layers of relevant DNNs using 8-bit, 4-bit, and 2-bit data sizes, respectively. Moreover, we showthat Bison-e enhances energy efficiency by 5× for string-matching tasks when compared to a RISC-V-based vector processingunit (VPU). We integrate Bison-e into a complete SoC based on RISC-V showing that it only accounts for a negligible 0.07% areaoverhead compared to the baseline architecture.We then propose Mix-GEMM, a hardware-software co-designed architecture accelerating quantized DNNs, supporting arbitrarydata sizes ranging from 8-bit to 2-bit, including mixed-precision computations. On the software side, we introduce a library thatenhances the existing BLIS framework and exploits custom RISC-V instructions to allow for high-performance matrix-matrixmultiplication on CPU architectures. On the hardware side, Mix-GEMM leverage on the Bison-e microarchitecture to performSIMD computations among narrow integers, with performance scaling as the computational data sizes decrease. Ourexperimental evaluation, conducted on representative quantized CNNs and targeting edge and mobile CPUs, demonstrates thata RISC-V-based edge SoC incorporating Mix-GEMM achieves up to 1.3 TOPS/W in energy efficiency and up to 13.6 GOPS percore in throughput, surpassing the performance of the OpenBLAS framework running on a commercial RISC-V-based edgeprocessor by a factor ranging from 5.3× to 15.1×.Furthermore, synthesis and PnR of the enhanced SoC in 22nm FDX technology shows that Mix-GEMM accounts for only 1% ofthe overall SoC area.We finally explore a novel hardware microarchitecture called Flex-SFU, acceleration complex DNN activation functions. Flex-SFUexpands the set of functional units within deep learning VPUs, used as general-purpose co-processors alongside the main matrixmultiplication units of DNN accelerators targeting HPC and cloud computing. Flex-SFU leverages non-uniform piecewiseinterpolation and supports multiple data formats. Thanks to these features, Flex-SFU achieves an average improvement of 22.3×in mean squared error (MSE) compared to previous piecewise linear (PWL) interpolation approaches. We evaluate Flex-SFUusing over 600 computer vision and NLP models, demonstrating an average end-to-end performance improvement of 35.7%compared to the baseline AI hardware accelerator, while only introducing a 5.9% area and 0.8% power overhead.
  
• RODRIGO MUÑOZ, SANTIAGO: A double full-stack architecture for multi-core quantum computers
  
  Author: RODRIGO MUÑOZ, SANTIAGO
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Deposit date: 02/10/2023
  Reading date: pending
  Reading time: pending
  Reading place: pending
  Thesis director: ABADAL CAVALLÉ, SERGI | ALARCON COT, EDUARDO JOSE
  Committee:
       PRESIDENT: CACCIAPUOTI, ANGELA SARA
       SECRETARI: GARCIA SAEZ, ARTURO
       VOCAL: SEBASTIANO, FABIO
  Thesis abstract: Despite its tremendous potential, it is still unclear how quantum computing will scale to satisfy the requirements of its most powerful applications. Continued progress in the fabrication and control of qubits is certainly required. However, there are hard limits to the number of qubits that can be integrated into a single chip. Multi-core quantum computing has been identified as a solution to the scalability problem of quantum computing, and included in the development roadmaps of the leading industry. Nevertheless, interconnecting quantum chips is not trivial, as quantum communications have their share of quantum weirdness. Quantum data cannot be copied, and decoherence is an unforgiving noise source for every qubit transfer, where every extra nanosecond counts and retransmission is physically impossible. Despite all these challenges, a comprehensive approach to quantum computer design based on multi-core architectures that leverages all the potential of quantum communications is crucial to unlocking the scalability issues.In this context, the present thesis aims to lay the foundations of such a communications-enabled multi-core quantum computing architecture, as a proposed vision for the ultimate success of quantum computing. Our goal is to design a multi-core architecture that entangles computing and communication with a complete understanding of their intertwining requirements. In this way, while putting together dozens of quantum cores (i.e. thousands or millions of qubits collaborating), we alleviate the requirements for control circuits and improve qubit isolation.In order to achieve this goal, we tackle three main tasks. First, we propose a layered approach for a double full-stack comms-enabled many-core quantum computer architecture (chapter 2), aligned with our vision. We aim to provide the basis for an architecture that may be technology-agnostic and intertwine quantum computing and communications.Secondly, using design space exploration, we carry out a scalability and feasibility study of multi-core quantum architectures. The first approach used analytical formulations (chapter 4), while at the end of the thesis, leveraging all the acquired knowledge, code-base analysis, and fully-fledged network simulations are employed, run within a framework developed also for this work (chapter 7). The results of the exploration let us also compare different existing qubit and quantum communication technologies (section 4.4.2). This work might facilitate future work for providing design guidelines and optimal operation ranges for efficient and scalable multi-core quantum computers.Finally, all this work needs to be backed by a study on short-range quantum communications. In particular, we have developed a model of quantum teleportation as a fitting candidate for inter-core communication technology (chapter 5). Moreover, we perform a thorough qubit traffic analysis on several algorithms and architectures that helps us see the bottlenecks and inefficiencies of such a network (sections 6.1 to 6.3). This leads to a latency and throughput analysis with real traffic together with the dimensioning of networking resources, completed by using a fully-fledged simulator developed for this thesis that models with high fidelity the different parts of a multi-core quantum computer (section 7.1). In addition, we have started the development of an efficient MAC protocol specific to our use case (section 6.4), which we believe will complete the architecture design and communications modeling.With the results of this thesis, we hope to contribute with design guidelines that may enable multi-core quantum architectures to unleash the potential of quantum computing.
  

Last update: 04/10/2023 04:30:30.

List of defended theses by year

• AHMADIAN, SEYED MORTEZA: Artificial intelligence solutions for quantum communications
  
  Author: AHMADIAN, SEYED MORTEZA
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 16/06/2023
  Thesis director: VELASCO ESTEBAN, LUIS DOMINGO | RUIZ RAMÍREZ, MARC
  

  Committee:
       PRESIDENT: APARICIO PARDO, RAMÓN
       SECRETARI: JUNYENT GIRALT, GABRIEL
       VOCAL: NADIMI GOKI, PANTEA
  Thesis abstract: This Ph.D. thesis focuses on the application of intelligent models to Discrete-Variable Quantum Key Distribution (DV-QKD) protocol.The first objective focuses on providing a method for AI-based polarization drift compensation for transmitting discrete photons in a quantum channel. In order to fully achieve this goal, we need to tackle two specific sub-goals. Firstly, AI based State of Polarization (SOP) tracking is designed to compensate polarization drift in quantum channels. The SOP trajectory is predicted ahead under different environmental events that causes SOP distortion. Here, we use SOP recognition procedure at the quantum receiver and evaluate different interpolation methods for planning the compensational rotation. On the other hand, a heuristic-based rotation manager adapted for BB84 protocol was proposed to minimize the number of rotations applied to the receiving photons in order to prevent the reduction in key rate generation.The second objective focuses on checking the feasibility of the proposed method for polarization compensation in DV-QKD systems. Here, issues mainly are: a) the strict requirements for quantum transmitters and receivers and, b) the need for carefully selecting the fibers supporting the quantum channel to minimize the environmental effects that could dramatically change the SOP of the photons. In order to fully achieve this goal, an experimental testbed which is being used in the polarization encoded QKD system has been set up. Also, software modules are needed for an intelligent QKD system tocompensate for the uncalibrated testbed¿s components. Finally, analysis of the experimental results and KPI measurements including testbed validation, fine tuning, and issue solving are evaluated.The final objective targets developing a Digital Twin (DT) that can address the shortcomings of the DV-QKD system, which cannot be achieved through the use of AI-based systems in the first goal. In order to fully achieve this goal, we need to address two specific sub-goals. On the one hand, the improvement of AI based SOP compensation using the DT. Specifically, DT helps to select, among different AI models, which one needs to be used in the receiver in order to take proper actions against different detected environmental events. On the other hand, DT targets at discerning eavesdropping actions from environmental events in quantum channel as both increase the quantum Bit Error Rate (qBER).
  

• ALCAIDE PORTET, SERGI: Hardware/software solutions to enable the use of high-performance processors in the most stringent safety-critical systems
  
  Author: ALCAIDE PORTET, SERGI
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 19/07/2023
  Thesis director: KOSMIDIS, LEONIDAS | ABELLA FERRER, JAIME
  

  Committee:
       PRESIDENT: ITURBE LILI, XABIER
       SECRETARI: CANAL CORRETGER, RAMON
       VOCAL: RECH, PAOLO
  Thesis abstract: Future Safety-Critical Systems require a boost in guaranteed performance in order to satisfy the increasing performance demands of the state-of-the-art complex software features. Ar1 approach to achieve these performance requirements is the usage of High-Performance Computing (HPC) components which can deliver more computation power than current safety­ critical components. However, the dependability support of these HPC components are not the same as that for the safety-­ critical components, so HPC components can jeopardize the functional safety of the entire system, especially since some of the highest-criticality functionalities maybe executed entirely on top of these components (e.g., neural networks in a Graphical Processing Unit (GPU)). Based on the safety requirements of performance-hungry critical applications, such as those for an autonomous operation, these HPC components must comply with the highest criticality levels, hence including the required dependability support. The overarching goal of this thesis is to present techniques to achieve that in different HPC components. In particular, we focus on GPUs and multicores. The techniques presented aim at providing diverse redundant execution, as needed to avoid Common Cause Failure (CCF)s, which are those defeating safety measures (e.g., pure redundancy) as a consequence of a single-point fault (e.g., a fault affecting both redundant instances identically). Such a solution is comparable to the lockstep execution employed on safety-critical processors.The first set of contributions of this thesis focuses on enabling diverse redundant execution on a single GPU. We propose two different solutions: (1) a slight hardware modification affecting the internal scheduler of the GPU and (2) a software-only approach that requires knowledge of the hardware resources of the GPU. In these contributions, we also analyze the staggering created due to the CPU-GPU inherent interaction.Finally, the last contribution relates to multicore systems. Similarly to the previous contributions, we focused on enabling diverse redundant execution on this component. However, executing a workload twice in two different cores is something relatively simple with modern programming models (e.g., OpenMP, OpenMPI). The real challenge is in using the limited observability and controllabilitychannels to maintain and guarantee the (time) diversity between these two redundant executions, like the lockstep approach. Note that lockstep is an expensive approach that hijacks halfofthe cores, which are non-visible to the user and cannot be used for non-critical applications. Instead, if a flexible software-only solution for COTS multicores existed, all cores could be used by non-critical applications when not needed for the safety-critical ones. Thus, maximizing their utilization. To tackle this challenge, we proposed a software-only solution with small requirements that can be met by most existing COTS multicore.
  

• ALMASAN PUSCAS, FELICIAN PAUL: Leveraging graph neural networks for optimization and traffic compression in network digital twins
  
  Author: ALMASAN PUSCAS, FELICIAN PAUL
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 17/07/2023
  Thesis director: CABELLOS APARICIO, ALBERTO | BARLET ROS, PERE
  

  Committee:
       PRESIDENT: CASAS HERNANDEZ, PEDRO
       SECRETARI: MANGUES BAFALLUY, JOSEP
       VOCAL: LEONTIADIS, ILIAS
  Thesis abstract: In recent years, several industry sectors have adapted the Digital Twin (DT) paradigm to improve the performance of physical systems. This paradigm consists of leveraging computational methods to build high-fidelity virtual representations of a physical system or entity. The virtual replica accurately simulates or models the behavior of the physical system without altering its behavior in the real world. Since its inception, the DT has attracted the interest of both academia and industry which can be observed by the growing number of publications, processes, standards and concepts.The networking community has adapted the DT paradigm with the objective of achieving efficient control and management in modern communication networks. In this context, the Network Digital Twin (NDT) is a renovated concept of classical network modeling tools whose goal is to build accurate data-driven network models. NDTs can be applied to many fundamental networking applications. For example, the NDT allows network operators to design novel network optimization solutions, to perform troubleshooting, what-if analysis, or to plan network upgrades taking into account the network¿s expected user growth. Since the interaction between the network operator with the NDT does not require access to the real-world network, the aforementioned processes can be carried out in real-time, without jeopardizing the physical network.This dissertation aims to develop new efficient real-time optimization mechanisms leveraging NDTs. Existing network optimization techniques can be generally divided among optimizer-based solutions (e.g., CP, ILP), heuristics and Machine Learning-based (ML) solutions. Optimizer-based solutions are computationally intensive and they suffer from scalability issues where the optimization time and the problem instance size scale at different speeds. The methods based on heuristics are solutions designed by human experts, making strong assumptions and simplifications on the original problem to reduce its complexity and to make the problem tractable by humans. This is a lengthy process that makes solutions be far-from-optimal, achieving poor network performance at a high cost for the network operator. Finally, existing ML-based solutions need to re-train the ML model every time there is a change in the optimization scenario (e.g., link failure). However, training ML models is a costly process which impedes the application of such methods on real-time network optimization.The first part of this dissertation proposes an optimization architecture that integrates Graph Neural Networks (GNN) into Deep Reinforcement Learning (DRL). This architecture leverages the planning strategies of DRL and the generalization capabilities of GNNs to optimize over arbitrary network topologies in real-time without the need of re-training the DRL agent. The experimental results show that the DRL+GNN architecture is robust to operate in real-world topologies that largely differ from the scenarios seen during training. In our work, we evaluate the proposed architecture on two real-world network optimization scenarios. The first scenario is in optical transport networks and the second scenario is in IP networks.Training DRL agents and building NDTs requires storing large datasets that include a wide range of network states and configurations. However, the network size has been growing both in traffic volume and number of connected devices. Boosted by the deployment of 5G networks and the adaptation of new industry paradigms (e.g., Internet of things), the growing trend is expected to continue for several years. Consequently, storing such large volumes of network-related information can be challenging. The second part of this thesis proposes a new data compression method based on GNNs capable of exploiting spatial and temporal correlations naturally present in network traffic traces, outperforming widely used compression methods such as GZIP.
  

• CARDONA NADAL, JORDI: Practical strategies to monitor and control contention in shared resources of critical real-time embedded systems
  
  Author: CARDONA NADAL, JORDI
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 03/04/2023
  Thesis director: CAZORLA ALMEIDA, FRANCISCO JAVIER | HERNANDEZ LUZ, CARLES
  

  Committee:
       PRESIDENT: BEIVIDE PALACIO, JULIO RAMON
       SECRETARI: ROYUELA ALCÁZAR, SARA
       VOCAL NO PRESENCIAL: BENEDICTE ILLESCAS, PEDRO
  Thesis abstract: In the last decade performance needs in Critical Real-Time Embedded Systems (CRTES) domains like automotive, avionics, railway or space have been steadily on the rise due to the unprecedented computational power required for the new complex and performance-eager emerging applications. To meet these computational needs, CRTES industry has been increasingly resorting to high-performance multicore and manycore processors that can cater for the required performance in a cost-efficient manner. To that end, relatively simple bus-based multicore processor designs have been successfully deployed in general-purpose computing to provide good performance at low energy and area cost. However, these solutions quickly become ineffective with larger core counts as the bus becomes a major performance bottleneck. For this reason, bus-based designs have started migrating to Networks on Chips (NoCs) designs like trees, rings, meshes or torus topologies, which are being increasingly adopted in CRTES to offer multiple point-to-point connections.Software timing is a paramount concern in the design and deployment of CRTES as correctness of the provided functions is typically not only determined by the delivered results, but also by the time at which those results are delivered. Domain-specific safety standards advocate for the adoption of software timing analysis techniques in the software development life-cycles as a necessary step to ascertain and guarantee all functions in the system execute timely and to prevent timing misbehavior to arise at run time. Timing concerns become particularly relevant to support three main phases in the CRTES development process: Verification Phase (budgeting), Validation Phase (testing) and Enforcement.Performing an efficient, industrial-quality timing analysis in the presence of complex multicore and manycore processors with complex hardware features like NoCs is complicated by the non-negligible timing interference arising when multiple cores contend in parallel to the same shared hardware resources through the interconnects. Multicore interference causes the execution time of a task to depend on the other tasks in the system, making it extremely difficult to characterize software timing in a trustworthy yet tight manner.The main challenges arise (i) in the budgeting phase, when deriving tight upper-bounds to the worst theoretical contention impact that requests can experience in traversing the NoC from their source to their destination, and (ii) in the validation phase, when tracking the actual multicore contention tasks generate on each other.This Thesis addresses the problem of enabling efficient and effective contention analysis and characterization in NoC-based CRTES. While most of the works have focused on the verification phase, this Thesis addresses all three main steps in the overall software timing analysis in manycore processors. On the verification side, we propose EOmesh and NoCo solutions that optimize wormhole NoCs¿ (wNoCs) configuration to lower WCET and obtain tight WCET estimates while improving CRTES performance. On the validation phase, we propose a technique to breakdown the contention that cores generate each other in wNoCs. To that end, we introduce a Golden Reference Value (GRV) on top of a PairWise Contention (PWC) metric that accurately identifies contention sources in wNoCs and provides a detailed multi-dimension contention breakdown, and a comparative analysis on the evolution of source contention identification in wNoCs. Finally, we cover a fundamental requirement in the enforcement phase by proposing MCCU, a software/hardware solution that performs fine-grain tracking of cores accesses in shared resources and enables, via configuration registers, preventing cores to cause more interference on its contenders than budgeted by the system designer.
  

• CASTELL UROZ, ISMAEL: A novel approach to web tracking detection and removal with minimal functionality loss
  
  Author: CASTELL UROZ, ISMAEL
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Article-based thesis
  Reading date: 06/07/2023
  Thesis director: BARLET ROS, PERE
  

  Committee:
       PRESIDENT: PEDERSEN, JENS MYRUP
       SECRETARI: CARELA ESPAÑOL, VALENTÍN DANIEL
       VOCAL: HADDADI, HAMED
  Thesis abstract: Web tracking technologies are extensively used to collect huge amounts of personal information from our online activity, including the things we search for, the sites we visit, the people we contact, or the products we buy. Although it is commonly believed that such big data sets are mainly used for targeted advertising, some recent works have revealed that they are actually exploited for many other purposes, including price discrimination, financial assessment, determination of insurance coverage, background scanning, and even identity theft. Contrary to popular belief, such information is not only collected by big Internet players, such as Google and Facebook, but also by more shady and unknown companies called data brokers. Data brokers are pervasive on the current Internet, and their only purpose is to silently collect and aggregate large amounts of personal information. This information is then used to build individual profiles (often of low quality) about us, which are sold to the highest bidder without our explicit knowledge or the option to revise their correctness. The main objective of this thesis is to research new countermeasures that can decrease or completely block web tracking systems running in the background. For this purpose, the thesis has three objectives: (i) develop a new measurement system that can collect information in a bigdata environment such as the Internet; (ii) research new methodologies to automatically detect unknown web tracking technologies while minimizing website functionality loss; and (iii) apply the research results obtained in order to create actual tools that can be useful for the different actors concerned about privacy. This manuscript presents a compendium of publications that address all the objectives presented.In order to handle the first objective, we developed a new framework called Online Resource Mapper, which is able to collect complete online data sets, including millions of websites with al their internal URLs and online resources. In addition, we also study the impact in performance and quality of experience of content blockers, the most popular current privacy-protectiontechnology. The second objective is tackled by means of three different publications presenting new ways to discover unknown web tracking systems. The first work presents an alternative to content blockers that potentially fixes their biggest vulnerability: the lack of adaptation to detect new web tracking URLs not present in the pattern lists. Our solution uses a deep neural network to discover with a 97% accuracy patterns that can be used to detect new tracking URLs. Going one step further, instead of looking at the URL, we decide to inspect the actual code of the website to discover not only tracking based on URL similarity, but completely new web tracking methods. Our first proposal, called TrackSign, uses the combination of a heuristic code partition model with a novel three-layer network graph in order to discover new web tracking systems. Our method achieves 92% detection accuracy, and it is one of the first approaches to do it in an automatic and generic fashion. Our last publication on the topic presents an evolution of TrackSign, called ASTrack, that addresses its main vulnerability, the false negatives obtained when websites obfuscate their internal resources with code renaming techniques. ASTrack uses the structure of the code instead of the code itself to identify web tracking systems shared by multiple websites. Moreover, ASTrack can exclusively remove the web tracking code while maintaining the rest of it intact, which minimizes functionality loss problems as a result of blocking complete resources. Lastly, in order to address the third objective, we shared publicly the results obtained during our experiments first in the form of a web tracking data set including about 75 million URLs and 45 million labeled online resources, and secondly in a new ePrivacy observatory called ePrivo.
  

• CRUZ DE LA CRUZ, STALIN LEONEL: Scaling deep learning workloads. Applications in computer vision and seismology
  
  Author: CRUZ DE LA CRUZ, STALIN LEONEL
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 06/07/2023
  Thesis director: TOUS LIESA, RUBÉN | OTERO CALVIÑO, BEATRIZ
  

  Committee:
       PRESIDENT: MARTI ESCALE, RAMON
       SECRETARI: CANAL CORRETGER, RAMON
       VOCAL: CARRERAS COCH, ANNA
  Thesis abstract: Deep learning techniques have an enormous impact on the state-of-the-art in many fields, such as computer vision, natural language processing, audio analysis and synthesis, and many others. The increasing computing power, the increasing amount of available data, and the algorithms' evolution foster this impact. On the one hand, this thesis applies Deep Learning techniques to large parallel systems to train and validate Neural Networks models for different applications. First, a technology stack to enable the distribution of deep learning workloads on a traditional High Performance Computing (HPC) setup such as the MareNostrum supercomputer is designed and evaluated. The key element of the deployed layered architecture is Apache Spark, which enables to isolate machine-learning applications from the particularities of the infrastructure, in this case, the MareNostrum supercomputer. The deployment of Spark-enabled clusters over MareNostrum is not trivial and it has done with the help of Spark4MN, a custom interoperability layer. On top of this stack (Marenostrum, Spark4MN and Spark) a deep learning specific layer is placed, DL4J. The goal is to provide insights into how the job configuration on a traditional HPC setup can be optimized to efficiently run this kind of workloads. The derived conclusions should be useful to guide similarly complex deployments in the future. Second, in a derived work, a use case is explored. We design and train deep CNNs for annotating and filtering images from social media (Instagram and Twitter). We capture the images in real-time and processes them by multiple CNNs that automatically enrich their metadata with tags that describe their visual content and also how they fit the visual identity of a brand (VBI) . With this method, we have trained VBI classifiers for more than 10 real brands and more than 100 classifiers for generic description of social media images. On the other hand, this thesis applies Deep Learning techniques on a computer cluster to train multiple NN configurations employed for earthquake detection and location. First, we develop a new method called UPC-UCV, consisting of applying a convolutional neural network to single-station 3-channel waveforms for P-wave earthquake detection and source region estimation in north-central Venezuela. This part includes the build of a new dataset, CARABOBO, that has been made public for reproducibility and benchmarking purposes. Both the UPC-UCV network and the CARABOBO dataset are the first developed for this geographic region. The method obtains better results than the State of the Art (SOA), yielding higher detection accuracy (13.3 percentage point increase) for the new target seismicity. UPC-UCV achieves a 95.27% detection accuracy. Second, in a derived work, we focus on the source region estimation problem. Source region estimation is a relaxed version of the earthquake location problem that consists on, first, partitioning a study area into K geographic subdivisions and, second, attempting to determine to which one the earthquake epicenter belongs. In the previous work, we performed the partitioning with k-means. In this part, we experiment with a geographical subdivision provided by a seismologist, consisting on irregular polygons covering the main seismic faults of Venezuela. While the obtained results for a small number of geographic subdivisions are not better than the ones obtained with k-means clustering, the good results obtained with a large number of subdivisions (91.78% with K::;:; 10) outperform the k-means approach (66.10%). It should be noted that to obtain these results, the use of spatial-based techniques significantly improved the final model. This confirms the target hypothesis that the source region estimation accuracy is significantly increased if the geographical partitioning is performed considering the regional geophysical characteristics such as the tectonic plate boundaries.
  

• FERNÁNDEZ MUÑOZ, JAVIER: Software diagnostics for autonomous safety-critical control-systems based on artificial intelligence
  
  Author: FERNÁNDEZ MUÑOZ, JAVIER
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 18/07/2023
  Thesis director: ABELLA FERRER, JAIME | AGIRRE TRONCOSO, IRUNE
  

  Committee:
       PRESIDENT: HERNANDEZ LUZ, CARLES
       SECRETARI: RUBIO SOLA, JOSE ANTONIO
       VOCAL: ONWUCHEKWA, DANIEL LUCKY NDUBUISI
  Thesis abstract: Machine Learning (ML) systems allow the efficient implementation of functionalities that can be hard to program by traditional software due to the high spectrum of inputs that hinder the definition of a specific procedural rule set. This characteristic of ML systems has encouraged their adoption in applications such as object detection or image classification in several safety-related domains, which are subject to safety certification. This certification is usually achieved by adhering to traditional functional safety standards such as IEC 61508 or ISO 26262. However, these standards were not devised to accommodate technologies such as ML in safety-related systems due to their development process, which is based on probabilistic models generated from training data, as opposed to traditional software components coded from specifications. Additionally, new challenges arise due to the fact that these ML algorithms need to process large volumes of data, and this requires High-Performance Embedded Computing (HPEC) platforms with computing capabilities far superior to traditional safety systems, such as multicore devices and GPU accelerators. Current functional safety standards do not provide explicit guidance for the use of HPEC platforms in safety-relevant systems, and the inherent complexity of those highly parallel architectures challenges certifications. With this Thesis, we attempt to address these challenges and give a step forward towards the functional safety certification of safety control systems integrating ML components in HPEC platforms.
  

• FERRER CID, PAU: On the data quality improvement of air pollution monitoring low-cost sensor networks using data-driven techniques
  
  Author: FERRER CID, PAU
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 08/05/2023
  Thesis director: GARCÍA VIDAL, JORGE | BARCELÓ ORDINAS, JOSE MARIA
  

  Committee:
       PRESIDENT: GHANDEHARI, MASOUD
       SECRETARI: NAVARRO MOLDES, LEANDRO
       VOCAL: FORTINO, GIANCARLO
  Thesis abstract: Nowadays, authorities monitor the concentrations of regulated air pollutants in order to assist in decision-making processes, e.g., for the implementation of traffic restrictions, and mitigate the effects of air pollution. For this purpose, they deploy high-precision instrumentation, the cost of which makes the number of sensors deployed over a region very low. The advent of air pollution low-cost sensors (LCSs) has opened up the possibility of complementing the authorities' instruments with more measurement points.Unfortunately, LCSs present inaccuracies, which makes it difficult to include them in a regulated way for decision-making processes of authorities.In recent years, enabling technologies such as the internet of things (IoT) and machine learning (ML) have allowed the improvement of the data quality of LCSs. Therefore, this thesis is devoted to the improvement of the data quality of air pollution monitoring LCS networks focusing on two aspects; i) the improvement of data quality at node level using ML-based sensor calibration, and ii) theimprovement of the sensor network data quality by using measurements from the network sensors with a graph-based approach.In the first part of the thesis, the improvement of the data quality of individual sensors is investigated. First, it is evaluated how thesensor sampling affects the representativeness of the samples. Then, the use of ML techniques, both linear and nonlinear, for the in-situ calibration of LCSs is analyzed. The in-situ sensor calibration task can be seen as a supervised ML learning problem, so techniques such as multiple linear regression (MLR) or support vector regression (SVR) are evaluated. The evaluation shows hownonlinear techniques improve the quality of pollution estimates significantly. In addition, given the inaccuracies present in LCSs and the difference that exists from one sensor to another of the same manufacturer, the inclusion in the calibration of multiple sensors measuring the same pollutant is investigated. Thereby, the proposed multisensor calibration approach based on ML results inincreased calibration accuracy.The second part of the thesis focuses on the quality of the data reported by a sensor network once deployed over an area. A graph-based approach is proposed to describe the existing relationships between sensors using a graph topology and represent the network measurements as signals defined on the graph, as realized in the graph signal processing (GSP) field. First, differenttechniques have been evaluated to correctly learn the relationships between sensors in a network that can contain both LCSs and high-precision nodes. The most suitable option has proven to be the data-driven GSP model based on signal smoothness. Then, different signal reconstruction techniques coupled with the graph have been studied in order to reconstruct pollution measurements reported by different sensors in a network. Kernel-based techniques and those based on the weights of the Laplacian have been themost effective ones. Once these main components have been studied, a graph-based data reconstruction framework has been proposed for different post-processing applications that appear in LCS networks, e.g., missing value imputation and virtual sensing.The results have shown how this framework allows for dealing with a wide variety of applications and scenarios that can occur in this context with precision. Finally, another important aspect of this type of network has been addressed, which is the detection of outliers. The Volterra graph-based outlier detection (VGOD) has been proposed, using a graph learned from the data and a signalreconstruction model based on the Volterra series, to detect and locate outliers. Therefore, the proposed algorithm has been provento improve the monitoring and maintenance of heterogeneous air pollution sensor networks by identifying abnormal measurementsand malfunctioning sensors.
  

• IQBAL, MASAB: Techniques for efficient and secure optical networks
  
  Author: IQBAL, MASAB
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 24/03/2023
  Thesis director: VELASCO ESTEBAN, LUIS DOMINGO | FERREIRA PEDRO, JOAO MANUEL
  

  Committee:
       PRESIDENT: PROIETTI, ROBERTO
       SECRETARI: JUNYENT GIRALT, GABRIEL
       VOCAL: FÀBREGA SÁNCHEZ, JOSEP MARIA
  Thesis abstract: Optical communication systems are widely adopted and responsible for transporting data traffic from access to metro to core networks supporting society¿s information and communication functions. As the traffic growth is increasing more innovative and efficient optical networking solutions other than the existing ones are needed to provide the industry with long-term sustainable profits. Also, with the advent of quantum computers these networks are vulnerable to a variety of security threats. Thus, either additional means of making the networks secure are needed or quantum aided transportation of data signal is required. Considering the challenges of efficiency and security aspects of current optical networks, this PhD thesis aims to provide techniques for efficient and secure optical networks.The current data traffic pattern in different segments of the optical networks can be a key factor to make the architecture more efficient. These traffic patterns are usually served by deploying point-to-point (P2P) connections which might not be the most cost-effective solution in certain segments like access and metro aggregation. This PhD thesis studies technologies supporting point-to-multipoint (P2MP) connections to serve dynamic and heterogenous data traffic flows. A well-known technology known as Digital Subcarrier Multiplexing to implement P2MP connection is used as a benchmark to evaluate the performance of a novel technology called Optical Constellation Slicing, to cater the same dynamic and heterogenous traffic requirements. For a dynamic profile these two technologies are compared against the traditional technology supporting P2P. The analysis in terms of cost, efficiency of data throughput and architecture simplicity is provided all along. The potential of P2MP connections is demonstrated. To make the optical networks secure, the studies are carried out in two dimensions. Firstly, the vulnerability of the physical layer is targeted. To make the overall network more secure, methods for physical layer cryptography are studied. Secondly, quantum communication technology is investigated because it is inherently secured by the laws of quantum mechanics. For physical layer security, we propose LPsec (lightpath security) where we target providing a complete solution of security from key exchange methods at physical layer to investigate cryptographic techniques that can support encryption at line speed. LPsec tends to be secure according to current standard and introduces negligible delay in data transmission.Although quantum communication is inherently secure, it faces different challenges. We explore two such challenges in presence of no-cloning theorem i) qubit retransmission and ii) P2MP quantum communication (QP2MP). As qubits are prone to a variety of sources of noise, qubit retransmission can enhance the successfully transmission of qubits from source to destination. Similarly, QP2MP can enable multiparty quantum communication which is far less explored in discrete variable quantum systems. For these two tasks, we consider creating imperfect clones through Universal Quantum Cloning Machine. We propose a novel protocol Quantum Automatic Repeat Request (QARQ) inspired by its classical equivalent. We have shown than that QARQ can significantly increase the successful recovery of qubits. QP2MP communication is examined for direct transmission (DT)-which is currently implementable considering hardware availability, teleportation (TP)-which is the future of quantum internet, and telecloning (TC)-which is the combination of cloning and TP. In presence of different types of decoherences it has been shown that TC provides the best quality of the qubit state but it the most complex protocol in terms of quantum cost. After studying challenges in qubit transmission, we presented QQPSK, a quantum way to perform Quadrature Phase Shift Keying (QPSK). QQPSK makes classical data inhenrently secured.
  

• LIU, PEINI: Convergence of high performance computing, big data, and machine learning applications on containerized infrastructures
  
  Author: LIU, PEINI
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 17/07/2023
  Thesis director: GUITART FERNANDEZ, JORDI
  

  Committee:
       PRESIDENT: PIERSON, JEAN-MARC
       SECRETARI: BERRAL GARCÍA, JOSEP LLUÍS
       VOCAL: DJEMAME, KARIM
  Thesis abstract: The convergence of High Performance Computing (HPC), Big Data (BD), and Machine Learning (ML) in the computing continuum is being pursued in earnest across the academic and industry. We envision virtualization and containerization technologies can be the basis for the convergence, because they reside as bridges between applications and infrastructures and provide well-known advantages. However, challenges remain for this convergence at the containerization level due to the diversity of applications and hardware heterogeneity: in the infrastructure layer, virtualization/containerization must feature complete isolation of the applications in a multi-tenant environment, seamlessly and efficiently provide different resources, allow agile and fine-grain dynamic resource provisioning to orchestrate resource sharing in those environments, also integrate HPC and Cloud scheduling and resource management techniques, while providing fault tolerance, energy efficiency, and scalability. Moreover, in the platform layer, virtualization/containerization must fulfill applications requirements of portability and reproducibility by allowing the definition of encapsulated and customized diverse software stacks, and the efficient creation/termination of those software environments on demand. The general research question of this thesis is: How to leverage virtualization/containerization in both the infrastructure layer and the platform layer to support efficiently the convergence of HPC, BD, and ML applications while taking advantage of heterogeneous HPC and Cloud resources?To answer that question, firstly, we enable deployments of HPC, BD, and ML applications using containers that allow the definition of encapsulated and customized software stacks for each application and provide seamless and efficient access to different resources through different configurations. This is the basis of the convergence.Secondly, the challenge is to understand the performance impact of the various configurations and deployment options when using containers. Thus, we perform several detailed performance analyses of containerization deployment options for diverse containerized applications on different hardware. These performance analyses consider different containerization-level configurations, such as containerization technologies, granularities, affinities, and network interconnects. The obtained performance insights can be guidelines to derive placement policies when deploying applications to better utilize resources and achieve better application performance.Thirdly, we enable DevOps for developing, building, and deploying these containerized applications and managing containers in multi-tenant, dynamic context circumstances by establishing a platform, Scanflow-K8s, to help the users to develop faster their containerized applications, to enable the deployment options analyzed before to feature efficient deployments, and to bring autonomic computing for continuously managing applications. Scanflow-K8s features a multi-agent multi-layered architecture that enables the online supervision of the end-to-end life-cycle of ML workflows on Kubernetes, as well as the deployment of containerized HPC workloads.Finally, we leverage the knowledge learned from the performance analysis of the configuration and deployment of containerized HPC, BD, and ML workloads, and the availability of Scanflow-K8s, to conduct autonomic management policies to schedule or manage these applications. On the one hand, we implement policies in the agent to evaluate the autonomic management and online supervision of the end-to-end life-cycle of ML workflows. On the other hand, we propose fine-grained scheduling policies for containerized HPC workloads in Kubernetes clusters.
  

• VAVOULIOTIS, GEORGIOS: Advanced hardware prefetching in virtual memory systems
  
  Author: VAVOULIOTIS, GEORGIOS
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 12/09/2023
  Thesis director: ÁLVAREZ MARTÍ, LLUC | CASAS GUIX, MARC
  

  Committee:
       PRESIDENT: PNEVMATIKATOS, DIONISIOS
       SECRETARI: MARTORELL BOFILL, XAVIER
       VOCAL: ROS BARDISA, ALBERTO
  Thesis abstract: Despite groundbreaking technological innovations, the disparity between processor and memory speeds (known as Memory Wall) is still a major performance obstacle for modern systems. Hardware prefetching is a latency-tolerance technique that has proven successful at shrinking this bottleneck. Nearly all real-world µarchitectural designs employ various prefetchers.Consequently, hardware prefetching attracts a lot of research attention. Virtual memory has been vital for the success of computing due to its programmability and security benefits. However, virtual memory does not come for free since each memory access requires a translation from the virtual to the physical address space that incurs high latency and energy overheads. To alleviate these overheads, a hardware cache, named Translation Lookaside Buffer(TLB), is typically employed to store the most recently used translations. However, TLBs are limited in capacity, thus there are not adequate for assuring high performance.Processor vendors address the need for fast address translation by providing dedicated support for virtual memory (e.g.,multi-level TLBs, multiple page sizes). Despite the existence of such support, the advent of applications with large data and code footprints aggravates the pressure placed on the virtual memory subsystem, resulting in frequent page walks that deteriorate system's performance. This dissertation argues that hardware prefetching can attenuate the Memory Wall bottleneck in virtual memory systems. To support our claim, we design and propose fully-legacy preserving TLB prefetching schemes and exploit address translation metadata that are available at the µarchitecture to improve the effectiveness of the prefetchers operating in the physical address space. To reduce the overheads of frequent TLB misses due to data accesses, we propose a solution that consists of the Sampling-Based Free TLB Prefetching (SBFP) scheme and the Agile TLB Prefetcher(ATP). SBFP exploits the locality in the last-level of the page table to enhance the performance of TLB prefetching. ATP combines three prefetch engines while disabling TLB prefetching during phases that does not provide benefits. Across different benchmark suites, we show that ATP combined with SBFP improves performance over the best performing prior TLB prefetcher while reducing the page walk references to the memory hierarchy. Next, we argue that instruction address translation is an emerging bottleneck in servers. To support our claim, we characterize the TLB behavior of server workloads and provide evidence that instruction address translation is a bottleneck in servers. To attenuate this bottleneck, we propose Morrigan, the first instruction TLB prefetcher.Morrigan combines a sequential prefetcher with an ensemble of hardware Markov prefetchers that build variable length Markov chains out of the instruction TLB miss stream while using a new frequency-based replacement policy. Across a set of industrial server workloads, Morrigan provides great performance gains while eliminating the majority of the demand page walks for instruction accesses. Our last contribution improves the efficacy of cache prefetchers operating in the physical address space by exploiting modern support for large pages. We propose the Page-size Propagation Module(PPM), a µarchitectural scheme that transmits the page size information to the lower-level cache prefetchers and enables safe prefetching beyond 4KB physical page boundaries. We further design a module comprised of two prefetchers that both exploit PPM but drive prefetching decisions assuming different page sizes. Our experiments reveal that the proposed page size exploitation techniques provide great performance enhancements on various state-of-the-art cache prefetchers. ¿he proposals of this dissertation are fullylegacy-preserving, do not call for disruptive changes, do not require any OS involvement, and constitute practical solutions to real-world bottlenecks.
  

• VILARDELL MORENO, SERGI: Modelling and predicting extreme behavior in critical real-time systems with advanced statistics
  
  Author: VILARDELL MORENO, SERGI
  Thesis file: (contact the Doctoral School to confirm you have a valid doctoral degree and to get the link to the thesis)
  Programme: DOCTORAL DEGREE IN COMPUTER ARCHITECTURE
  Department: (DAC)
  Mode: Normal
  Reading date: 13/03/2023
  Thesis director: SERRA MOCHALES, ISABEL | ABELLA FERRER, JAIME
  

  Committee:
       PRESIDENT: BOLANCÉ LOSILLA, CATALINA
       SECRETARI: RADOJKOVIC, PETAR
       VOCAL NO PRESENCIAL: TRILLA RODRÍGUEZ, DAVID
  Thesis abstract: Critical Real-Time Embedded Systems (CRTES) are used in domains like transportation (e.g. avionics, automotive, space, and railway), healthcare, and industrial machinery. This subset of embedded systems requires undergoing a stringent Validation & Verification (V&V) process before they are allowed to enter in operation since any misbehavior can result in harm of humans or even fatalities. Software timing behavior is a key element to cover in the V&V process, providing with evidence that software runs timely. Software timing analysis, in turn, requires deriving bounds to each application task¿s execution time. These bounds are referred to as Worst-Case Execution Time (WCET) estimates. As CRTES implement more complex safety-related functionalities in every new product, more complex software and consequently more performant computing hardware is used to satisfy the high-performance requirements. The side effect, however, of using more complex hardware and software is challenging state-of-the-art software timing analysis techniques.Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques have been proposed to handle such hardware and software complexity providing tight and trustworthy WCET bounds (estimates). Specifically, Extreme Value Theory (EVT) has been used to provide with models for the most extreme occurrences in form of a probabilistic distribution. The output of the timing model is referred as a probabilistic WCET (pWCET). However trustworthy, EVT models can be cumbersome toapply and they sometimes can be exceedingly pessimistic which adds extra cost into timing budgets.This thesis investigates MBPTA techniques and develops novel methodologies within this framework in three distinct fronts. Firstly, by improving the tightness of pWCET models on sky-high quantiles with two models. A first one that combines risk analysis with EVT for a safe and accurate pWCET. And a second one that introduces Markov¿s Inequality to the pWCET estimation problem, which provides with trustworthy guarantees with less requirements for its correct application. Secondly,in order to boost the use of data coming from performance monitoring counters - increasingly used by MBPTA techniques to tighten estimates-, this thesis shows two mathematically-based ways of merging multiple disjointed readings based on order statistics and copula models. Finally, this thesis proposes a model for the contention of competing tasks, when the timing profile obtained is limited, that allows to provide with more extreme WCET scenarios based on the dependenciesbetween tasks.Summarizing, this thesis pushes the state-of-the-art forward in the V&V methodologies for CRTES in the framework of MBPTA in terms of WCET estimation and data gathering.
  

Last update: 04/10/2023 05:01:11.

Research groups

• ARCO-Microarchitecture and Compilers
• CAP-High Performace Computing Group
• CBA-Communications and Broadband Architectures Lab
• CNDS-Computer Networks and Distributed Systems
• CRAAX-Advanced Network Architectures Lab
• DAMA-UPC-Data Management Group
• GCO-Optical Communications Group
• ICARUS-Intelligent Communications and Avionics for Robust Unmanned Aerial Systems
• IMP-Information Modelling and Processing
• VIRTUOS-Virtualisation and Operating Systems

Research entities:

Teachers

• Alvarez Martinez, Carlos
• Ayguade Parra, Eduard
• Badia Sala, Rosa Maria
• Barcelo Ordinas, Jose Maria
• Barlet Ros, Pere
• Barrado Muxi, Cristina
• Becerra Fontal, Yolanda
• Bofill Soliguer, Pau
• Cabellos Aparicio, Alberto
• Canal Corretger, Ramon
• Careglio, Davide
• Cazorla Almeida, Francisco Javier
• Cela Espin, Jose M.
• Cerdà Alabern, Llorenç
• Corbalan Gonzalez, Julita
• Cortes Rossello, Toni
• Cruellas Ibarz, Juan Carlos
• Delgado Merce, Jaime M.
• Domingo Pascual, Jordi
• Espasa Sans, Roger
• Fernandez Jimenez, Agustin
• Freitag, Felix
• Gallego Fernandez, M. Isabel
• Garcia Almiñana, Jordi
• Garcia Vidal, Jorge
• Gil Gomez, Marisa
• Gonzalez Colas, Antonio Maria
• Gonzalez Tallada, Marc
• Guerrero Zapata, Manel
• Guitart Fernandez, Jordi
• Herrero Zaragoza, Josep Ramon
• Jimenez Castells, Marta
• Jimenez Gonzalez, Daniel
• Juan Hormigo, Antonio
• Labarta Mancho, Jesus Jose
• Larriba Pey, Josep
• Llaberia Griño, Jose M.
• Llorente Viejo, Silvia
• Llosa Espuny, Josep
• Lopez Alvarez, David
• Lopez Rubio, Juan
• Marin Tordera, Eva
• Martorell Bofill, Xavier
• Masip Bruin, Xavier
• Meseguer Pallares, Roc
• Monreal Arnal, Teresa
• Morancho Llena, Enric
• Moreto Planas, Miquel
• Navarro Moldes, Leandro
• Olive Duran, Angel
• Otero Calviño, Beatriz
• Pajuelo Gonzalez, Alex
• Parcerisa Bundo, Joan Manuel
• Pastor Llorens, Enric
• Perello Muntan, Jordi
• Reyes Muñoz, Angelica
• Rodriguez Luna, Eva
• Royo Valles, Maria Dolores
• Salami San Juan, Esther
• Sanchez Carracedo, Fermin
• Sanchez Lopez, Sergio
• Santos Boada, German
• Serral Gracia, Rene
• Sole Pareta, Josep
• Torres Viñals, Jordi
• Tous Liesa, Ruben
• Tubella Murgadas, Jordi
• Utrera Iglesias, Gladys Miriam
• Valero Cortes, Mateo
• Valero Garcia, Miguel
• Velasco Esteban, Luis Domingo
• Verdu Mula, Javier

• Alarcon Cot, Eduard
• Alvarez Marti, Lluc
• Arias Vicente, Marta
• Armejach Sanosa, Adria
• Arnau Montañes, Jose Maria
• Berral Garcia, Josep Lluis
• Cazorla Almeida, Francisco Javier
• de Almeida Amazonas, Jose Roberto
• Giro Nieto, Xavier
• Kosmidis, Leonidas
• Marinescu, Maria Cristina
• Oller Arcas, Antonio
• Peña Monferrer, Antonio Jose
• Perez Casany, Marta
• Riera Villanueva, Marc
• Silfa Feliz, Franyell Anotnio
• Vazquez, Mariano